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Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.


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Patent
Masayuki Nakamura1, Fujiya Ikuta1
02 Jun 1988
TL;DR: In this article, an extended bus controller includes a base module including at least a first peripheral control unit connected to a base bus, a central processing and controlling unit, and a memory unit.
Abstract: An extended bus controller includes a base module including at least a first peripheral control unit connected to a base bus, a central processing and controlling unit, and a memory unit; an extension module including at least a second peripheral control unit connected to an extended bus; a connection bus interconnecting the base bus of the base module and the extended bus of the extension module; a direct memory access control unit provided for at least one of the base module and the extension module for directly controlling data transfer between the first and second peripheral control units and the memory unit; a first master clock generator unit for supplying first master clocks to the direct memory access control unit and controlling the direct memory access control unit, the first master clocks having a first frequency determined by a data transmission delay time of at least one of the base bus, the connection bus and the extension bus, and by the performance of the first peripheral control unit and the memory unit; and a second master clock generator unit for supplying second master clocks to the direct memory access control unit and controlling the direct memory access control unit, the second master clocks having a second frequency determined by a data transmission delay time of at least one of the base bus, the connection bus and the extension bus, and by the performance of the second peripheral control unit and the memory unit.

28 citations

Patent
18 May 1999
TL;DR: A bus arbitration system uses different arbitration rules at different times, by periodically changing the priority order of the bus masters, by masking further bus requests from a particular bus master for a certain interval each time that bus master is granted the use of the buses.
Abstract: A bus arbitration system uses different arbitration rules at different times, by periodically changing the priority order of the bus masters; by masking further bus requests from a particular bus master for a certain interval each time that bus master is granted the use of the bus; by masking requests from bus masters other than a central processing unit for certain intervals while the central processing unit is processing an interrupt; by raising the priority of a particular bus master if a bus request from that bus master remains unacknowledged for a certain interval; or by ignoring bus requests from the central processing unit while another bus master is performing a certain process.

28 citations

Journal ArticleDOI
TL;DR: This paper seeks to take the bus network of Beijing as an example and mainly use space L and space P to analyze the network topology properties and shows that the network is a scale-free network and an assortative network with 46 communities.
Abstract: The transport network structure plays a crucial role in transport dynamics. To better understand the property of the bus network in big city and reasonably configure the bus lines and transfers, this paper seeks to take the bus network of Beijing as an example and mainly use space L and space P to analyze the network topology properties. The approach is applied to all the bus lines in Beijing which includes 722 lines and 5421 bus station. In the first phase of the approach, space L is used. The results show that the bus network of Beijing is a scale-free network and the degree of more than 99 percent of nodes is lower than 10. The results also show that the network is an assortative network with 46 communities. In a second phase, space P is used to analyze the property of transfer. The results show that the average transfer time of Beijing bus network which is 1.88 and 99.8 percent of arbitrary two pair nodes is reachable within 4 transfers.

28 citations

Patent
05 Mar 1986
TL;DR: In this paper, a slave device detecting system utilizes the past history of devices connected to a data bus to optimize the time required to re-establish communications, where the master controller senses a condition that requires an assessment of devices on the bus, it examines the addresses of previously connected devices at more frequent time intervals than it does for addresses that were not previously associated with connected devices.
Abstract: A slave device detecting system utilizes the past history of devices connected to a data bus to optimize the time required to re-establish communications. Whenever a master controller senses a condition that requires an assessment of devices on the bus, it examines the addresses of previously connected devices at more frequent time intervals than it does for addresses that were not previously associated with connected devices. In a preferred approach, all valid addresses can be examined in a sequential fashion, and the address of the previously connected device can be examined at every fifth or tenth position in the sequence. With such a technique, a device will be detected much faster once it has returned to the bus.

28 citations

Patent
Richard S. Grau1
25 Feb 1981
TL;DR: An asynchronous interface adapter for interfacing two bidirectional data buses is presented in this paper, which provides bus requests and grant logic, parity checking, time of day clocking, and is adapted to handle variable-length bus messages with the message bytes being carried in a bit-parallel byte-serial form.
Abstract: An asynchronous interface adapter for interfacing two bidirectional data buses. Data transfer between buses may occur simultaneously with provision made for storing bus data from a first bus until a receiver on the second bus is available. The adapter provides bus requests and grant logic, parity checking, time of day clocking, and is adapted to handle variable-length bus messages with the message bytes being carried in a bit-parallel byte-serial form, asynchronously and generally in a bidirectional manner.

28 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202229
202192
202093
201999
2018108