Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.

Integrated circuit for coupling a microcontrolled control apparatus to a two-wire bus

Abstract: An integrated semiconductor circuit for an electronic control unit has a microcontroller with a bus protocol function for communicating with other microcontrolled control units via a Controller Area Network (CAN) by way of a two-wire bus. The invention includes a bus-fault-tolerant transceive function which permits communication even when a bus fault is present. A bus fault recognition and response device disconnects the bus from its normal connections and alters its termination characteristics when a fault is detected.

Bus system, printed circuit board, signal transmission line, series circuit and memory module

Abstract: There are provided plural synchronous RAMs, a memory controller, a bus for inputting the signal output from the memory controller 1a to the synchronous RAMs, and a bus for inputting the signals output from the synchronous RAMs to the memory controller. Each of the buses has a main line and two stub lines connected to the trunk like. Each of the synchronous RAMs is connected to the corresponding stub line so that the sum of the bus length of the bus between the synchronous RAM and the memory controller and the bus length of the bus between the synchronous RAM and the memory controller is substantially constant among all of said synchronous RAMs. Therefore, the signal transmission time between the bus master and the plural bus slaves can be shortened without increasing the number of pins of the bus master while keeping the signal transmission time substantially constant among the plural bus slaves.

Method and apparatus for configuring a bus-to-bus bridge

Abstract: An information processing system includes a processor for processing information; a processor bus, a first expansion bus; a host bridge for coupling the processor bus to the first expansion bus; a second expansion bus; a first bus bridge for coupling the first expansion bus to the second expansion bus; a plurality of input/output (I/O) devices coupled to the second expansion bus; and a first storage device for storing a first set of configuration data for the plurality of I/O devices; a second storage device for storing additional configuration data. The first storage device includes a register for storing a pointer for pointing to addresses in the first storage device for forwarding addresses sent from the processor to the I/O devices.

Direct memory access apparatus and methods for transferring data between buses having different performance characteristics

Abstract: Methods and apparatus are disclosed for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ("CPU") is attached, and a second bus, to which a second set of relatively lower performance devices is attached. More particularly the invention accomplishes the transfer function in a manner that facilitates communication between the first and second set of devices from the comparatively lower performance of the second set of devices. Direct memory access ("DMA") apparatus and methods are disclosed, including a set of direct memory access channels. The DMA channels may be used to transfer data between the high performance channel (hereinafter referred to as the "Local Bus") coupled to the CPU in a reduced instruction set computer (RISC) system and a typically lower performance, peripheral bus (hereinafter referred to as a "Remote Bus"). The resulting DMA interface between the Local Bus and a Remote Bus permits a wide performance range of standard peripheral devices to be attached to the RISC system in a manner that does not limit system performance. The noval DMA may also be used as part of a data transfer controller (DTC) having other components, such as I/O ports, or may be used independently for transferring data between unmatched buses in, for example, computer systems, data transmission systems and the like.

Method for transmitting bus commands and data over two wires of a serial bus

Abstract: A low power, single master, variable clock rate, daisy-chainable, serial bus connects a bus dispatch (master) to a chain of one or more daisy-chained peripheral devices (slaves). The bus has a bidirectional serial data line, a bidirectional clock line, unidirectional interrupt line, power and ground lines. All bus transactions over the bus occur under bus dispatch commands. If a peripheral device interrupts the bus dispatch, bus dispatch issues commands over the bus to determine which device caused the interrupt and what service is being requested by the device. The bus dispatch may then turn control of the data and clock lines over to the peripheral device for a limited amount of time depending on the service requested. New peripheral devices can be connected onto the bus and unused peripheral devices can be disconnected from the bus while the bus is operating without causing a bus failure. Similarly, bus dispatch may enter a low power sleep mode from which it may be awakened by a peripheral device. In some embodiments, additional lines such as battery charging lines and/or signal lines for other serial buses such as RS-232 and RS-422 are provided.