Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.

Management communication bus for networking devices

Abstract: A management communication bus for enabling management of network devices in a network system. The network system includes at least one bus master device and at least one slave device, where the bus master and slave devices are distributed within the network devices. Each network device includes a slave device or a bus master device or both. The bus includes several conductors for state signals for defining four states for arbitration, for slave identification, for asserting an address and for asserting data corresponding to the address. The bus further includes several conductors for data signals for transferring information data depending upon the different states, where the information data includes bus request, slave identification, the address and the data corresponding to the address. Each bus master includes an interface to the bus to step through each of the states for controlling each cycle. Each bus master and slave device includes an identification number with a predetermined priority.

Multiprocessor system having local write cache within each data processor node

Abstract: A multiprocessor data processing system (10), and a method of operating same, so as to provide efficient bandwidth utilization of shared system resources (24, 26). The system includes a plurality of processor nodes, each of which includes a data processor (22a, 28a). A first step of a method buffers data written by a data processor to a first bus (23a), prior to the data being transmitted to a second bus (32). Also buffered are byte enable (BE) signals generated by the data processor in conjunction with the data written by the data processor. A next step performs a main memory (26) write operation by transmitting the buffered data to the second bus; responsive to the stored BE signals, also transmitting a control signal for indicating if a memory write is to be accomplished as a read-modify-write (RMW) type of memory operation; and transmitting the stored BE signals to the second bus. A further step couples the data, the RMW signal, and the BE signals from the second bus to a third bus (24) for reception by the main memory.

Bus architecture employing varying width uni-directional command bus

Abstract: A processor-memory bus comprises a command portion for transmitting addresses and commands, having a unidirectional input portion for transmitting commands to a central repeater unit, and a unidirectional broadcast portion for broadcasting commands from the repeater. The input portion comprises a plurality of links running from different devices, wherein each link is less than the full width of the broadcast bus portion. A command is transmitted over the input portion in a plurality of bus cycles, and broadcast over the broadcast portion in a single bus cycle. Since multiple input links connect to the central command repeater, it is possible to keep the broadcast bus full notwithstanding the fact that multiple bus cycles are required to transmit an individual command on the input portion. Preferably, the links are arranged hierarchically, from processors to local repeaters, from local repeaters to the central repeater, and back again. Preferably, the central repeater globally arbitrates the bus, and once the bus is granted, the command propagates along each link at pre-defined clock cycles from bus grant. In the preferred embodiment, addresses/commands and data are transmitted on essentially separate paths having different topologies, and at different times, and are arbitrated separately.

Wake-up circuit for a remotely located vehicle control module

Abstract: A wake-up circuit is provided for a vehicle control module interconnected via a bus network to a vehicle data communication system of a motor vehicle. The wake-up circuit includes an input voltage source; a bus detection stage for detecting bus activity on the bus network, an input stage for supplying the input voltage, and an output stage for supplying an output voltage to the vehicle control module. In operation, the bus detection stage provides an input signal in response to detecting bus activity on the bus network. In response to receiving the input signal from the bus detection stage, the input stage supplies a voltage from the input stage to the output stage. The output stage in turn regulates the output voltage to the vehicle control module.

Method and apparatus for multiplexing signals from a bus bridge to an ISA bus interface and an ATA bus interface

Abstract: An apparatus and method for connecting a bus bridge to a plurality of bus interfaces are disclosed. The invention allows output lines on a bus bridge to be shared so that a minimal amount of dedicated pins are utilized. Signals on the bus bridge which need to be driven and received quickly are connected directly from the bus bridge to the bus interfaces. Signals on the bus bridge which do not need to be driven and received quickly are connected from the bus bridge to the bus interfaces though buffers. The invention allows the bus bridge to interface a high speed local bus and a plurality of I/O buses while satisfying the timing requirements of each of the I/O buses.