Topic
Bus network
About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.
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TL;DR: A distributed control approach based on multiagent negotiation is presented, wherein stops and buses act as agents that communicate in real-time to achieve dynamic coordination of bus dispatching at various stops.
Abstract: A distributed control approach based on multiagent negotiation is presented, wherein stops and buses act as agents that communicate in real-time to achieve dynamic coordination of bus dispatching at various stops. The negotiation between a Bus Agent and a Stop Agent is conducted based on marginal cost calculations. We present optimality conditions for the formulated problem, using a negotiation algorithm, which we derive, to coordinate bus holding at various stops. A comparison between the negotiation algorithm and other simple bus control strategies such as on-schedule and even-headway strategies made through simulations verifies the robustness and efficiency of our negotiation strategy to different transit environments, involving both stationary passenger arrivals as well as a variety of nonstationary passenger arrivals.
92 citations
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11 Oct 1979
TL;DR: In this article, a data processing system comprising an active and intelligent main store including a main memory, a main store controller for accessing the main memory in a manner allowing different address and data structures, and an auxiliary processor connected to the controller is described.
Abstract: A data processing system comprising an active and intelligent main store including a main memory, a main store controller for accessing the main memory in a manner allowing different address and data structures, and a main store bus connected to the controller. At least one processor of a first type is connected to the main store bus, this being an auxiliary processor for performing input-output and other operations. At least one processor of a second type also is connected to the main store bus, this being an execution processor for fetching, decoding and executing instructions. All or some of either or both of the auxiliary processors and execution processors may be different. A supervisory processor for initiating configuring and monitoring the system is connected to the main store bus. A communication bus is connected to the processors of the first and second types and to the supervisory processor. A diagnostic bus connects the supervisory processor to each of the processors of the first and second types. An input-output bus ensemble is connected to the supervisory processor and to each auxiliary processor. At least one device and associated device controller can be connected to the input-output bus ensemble. At least one direct memory access controller can be connected between the main store bus and the input-output bus ensemble.
92 citations
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04 Sep 2001TL;DR: While all five SoC bus architectures perform well, it is found that BFBA and CSBA perform the best for the OFDM transmitter and the MPEG2 decoder, respectively.
Abstract: The performance of a system, especially multiprocessor system, heavily depends upon the efficiency of its bus architecture. In System-on-a-Chip (SoC), the bus architecture can be devised with advantages such as shorter propagation delay (resulting in a faster bus clock), larger bus width, and multiple buses. This paper presents five different SoC bus architectures for a multiprocessor system: Global Bus I Architecture (GBIA), Global Bus II Architecture (GBIIA), Bi-FIFO Bus Architecture (BFBA), Crossbar Switch Bus Architecture (CSBA), and CoreConnect Bus architecture (CCBA). The performance of these architectures is evaluated using applications from wireless communications-an Orthogonal Frequency Division Multiplexing (OFDM) transmitter-and from video processing-an MPEG2 decoder. To increase performance, these bus architectures employ a pipelined scheme, resulting in improved throughput. While all five bus architectures perform well, we find that BFBA and CSBA perform the best for the OFDM transmitter and the MPEG2 decoder, respectively.
92 citations
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14 Nov 1996
TL;DR: In this paper, a bus architecture for use in a data communication system provides a communication path between processors and one or more external devices including (M+1) hierarchical processors, and each of the processors is categorized into one of N hierarchies with M and N being a positive integer larger than 1, respectively, and N is smaller than (M + 1).
Abstract: A bus architecture for use in a data communication system provides a communication path between processors and one or more external devices including (M+1) hierarchical processors. Each of the processors is categorized into one of N hierarchies with M and N being a positive integer larger than 1, respectively, and N is smaller than (M+1). The bus architecture includes a bus having N buses, each of the buses coupled to one or more processors of a hierarchy and (N-1) linking means, and each of the linking means for coupling a bus of a hierarchy to a bus of a next hierarchy.
92 citations
01 Jan 2001
TL;DR: In this article, the performance of a system-on-a-chip (SoC), especially a multiprocessor system, heavily depends upon the efficiency of its bus architecture.
Abstract: The performance of a system, especially a multiprocessor system, heavily depends upon the efficiency of its bus architecture. In System-on-a-Chip (SoC), the bus architecture can be devised with advantages such as shorter propagation delay (resulting in a faster bus clock), larger bus width, and multiple buses. This paper presents five different SoC bus architectures for a multiprocessor system: Global Bus I Architecture (GBIA), Global Bus I1 Architecture (GBIIA), Bi-FIFO Bus Architecture (BFBA), Crossbar Switch Bus Architecture (CSBA), and Coreconnect Bus architecture (CCBA). The pedormance of these architectures is evaluated using applications from wireless communications - an Orthogonal Frequency Division Multiplexing (OFDM) transmitter - and from video processing - an MPEG2 decoder. To increase performance, these bus architectures employ a pipelined scheme, resulting in improved throughput. While all five bus architectures perform well, we find that BFBA and CSBA perform the best for the OFDM transmitter and the MPEGZ decoder, respectively.
92 citations