Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.

Method for powering elements connected in a two-wire bus network transmitting both power supply and data information pulses

Abstract: The present invention relates to a powering method for elements connected in a two-wire bus type network wherein information frames of predetermined length are transmitted at predetermined times. The method consists of regularly sending on the two-wire bus a power supply pulse between the end of an information frame and the beginning of the next frame.

Bus arbitration system and method

Abstract: A bus arbitration system for use in a data processing system which operates on clocked cycles for determining priorities in accessing a system memory and one or more local memories associated with processor units is shown. Each of the processor units are operatively coupled through a local bus to its associated local memory. A system bus interconnects the processor units and local memories in parallel to the local bus and the system is connected to an input/output device and the system memory. The bus arbitration system monitors requests made by processor units or the input/output device for access to the system memory or a local memory during the clock cycle. A determination section of a bus arbitration module determines whether access is available over the system data bus or a local data bus. A priority logic section identifies the existence of a conflict due to one or more of the processor units and the input/output device requesting access over the system bus to either the system memory or the same associated local memory during the clock cycle and for granting a request to a selected one of the processor units or the input/output device for accessing either the system memory or one of the associated local memories over the system bus. When a processor unit is denied access to the system bus, and in the absence of a conflict in request for the same associated local memory, a request is granted to a processor unit to access its associated local memory over its local bus during the clock cycle.

Communications and control network having multiple power supplies

Abstract: A network (60) allowing for communication, sensing and control, comprising at least three nodes (70, 71, 75) interconnected by a bus (61) for conveying both power and data. The bus includes at least two power carrying conductors, which may be used to convey the data together with the power, and across which at least two power supplies (62, 63, 64, 65) are connected via respective source couplers (66, 67, 68, 69) at different points thereof. Preferably, there are connected to the nodes one or more payloads (72, 73, 76) that may be powered by local power supplies (74, 77) so as to provide greater fault-protection and flexibility.

Bus-to-bus read prefetch logic for improving information transfers in a multi-bus information handling system (bus-to-bus bridge for a multiple bus information handling system that optimizes data transfers between a system bus and a peripheral bus)

Abstract: A method and system for improving bus-to-bus data transfers in a multi-bus computer system is provided. The system includes a system bus having a slave device attached thereto, a peripheral bus having a master device attached thereto, and a host bridge connecting the two buses. The system bus permits burst read transfers of data stored in the slave device, wherein a single address phase is followed by several data phases, but only if the first address corresponds to a prescribed system bus boundary. The peripheral bus is not subject to address boundary limitations, instead permitting burst read transfers beginning at any address. The host bridge includes logic for decoding a first address asserted by the master device to determine if it corresponds to a system bus boundary. If it does not, the logic commences a first read pre-fetch non-burst transfer of a first set of data stored in the slave device beginning at the first address and ending at a system bus boundary, and temporarily stores this first set of data in a buffer. The logic then commences a second read pre-fetch burst transfer of a second set of data stored in the slave device corresponding to data stored between system bus boundaries, and temporarily stores this second set of data in the buffer, so that both of the temporarily stored first and second sets of data may be read by the master device over the peripheral bus in a single burst read transfer.

Apparatus and methods for home networking

Abstract: A multimedia data distribution system comprises a distribution system adapted to distribute and deliver Asynchronous Transfer Mode signals to the level of an individual home network bus, a micro-PBX connected to the distribution system and to the home network bus; and a converter connected to the home network bus and having an outlet adapted for connecting to conventional single media and multimedia electronic devices, such as telephones, personal computers, fax machines, television sets, and the like. The micro-PBX is adapted to translate between the public network data protocol and a Local Area data protocol on the home network bus, and to manage the home network bus as a Carrier Sense Multiple Access/Collision Detect (CSMA/CD) type bus, and the converter is adapted to convert signals on the home network bus to a form required by one of the single media and multimedia electronic devices. In an alternative embodiment of the invention signals on the home network are provided as high-frequency, spread-spectrum signals.