Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.

Bus arbitration controller

Abstract: A bus arbitration controller controls access of a plurality of asynchronous potential master devices to a unitary interconnecting bus by forming a distributed state machine of arbitration logic units in each of the potential master devices Each arbitration logic unit receives control signals by way of the unitary bus which are common to all the devices, each control signal being the logical OR of the corresponding signals from all other devices The control signals include a device address/priority number and a synchronization signal set The arbitration logic includes a priority resolver which awards bus access to a device having the highest address/priority number, and control logic which receives the common synchronization signal set and synchronizes the operation of the device in which the arbitration logic resides with all other devices contending for the unitary bus The control logic and the priority resolver are programmable array logic circuits

Time multiplexed bus matrix switching system

Abstract: Ports including at least input and output signal lines are collected into port groups. For each port group three separate clock synchronized time division switches are connected respectively to the input signal lines, bus highways and the output signal lines. All time division switches of the system are synchronized by a system clock and each one is controlled by its own storage of selected addresses in time slot order. A plurality of bus highways is provided and the input time division switch connects signals to a specific bus highway of the system. A second time division switch selects the bus highway for connection to the output section of the port group. A third time division switch selects the output port to which the selected bus highway is connected. In one embodiment the bus highways directly connect the port groups. In another, a central inter-connect matrix is provided to make the connection between the first and second time division switches.

Free-space star-coupled optical data bus

Abstract: A free-space passively star-coupled optical data bus uses uniform uncollimated transmission light communicating data among a plurality of transmitter and receiver paired transceiver nodes of respective communication subsystems for communicating data from one transmitting node simultaneously to each of all of the remaining receiving nodes, the data bus being defined by a transmission volume having peripheral optical ports for optically interfacing the transceivers nodes to the free-space communication transmission medium having a distribution means to distribute the light and provide a variety of data bus configurations each supported by protocol addressing and optical modulation for connectorless communications for improved reliability and reduced costs especially well-suited for conference room, office, and spacecraft applications.

Time multiplexed processor bus

Abstract: A multi-master processor bus and a method of processing data which permits multiple microprocessors to communicate freely and inexpensively among themselves and various system resources. The bus uses a multiphase clock and latches to provide time slice signals to sequentially activate each processor, one at a time in a repetitive sequence. The bus includes cables and terminals for each of the cables with means for interconnecting each of the modules in series daisy chain fashion to selected cables.

Fault-Tolerant Multiprocessor Link and Bus Network Architectures

Abstract: This paper presents a general class of regular networks which provide optimal (near-optimal) fault tolerance.