Topic
Bus network
About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.
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24 Feb 1994TL;DR: In this paper, the authors propose a coherency scheme for a system having a bus, a main memory, and an access controller for accessing main memory in response to transactions received on the bus.
Abstract: A coherency scheme of use with a system having a bus, a main memory, a main memory controller for accessing main memory in response to transactions received on the bus, and a set of processor modules coupled to the bus. Each processor module has a cache memory and is capable of transmitting coherent transactions on the bus to other processor modules and to the main memory controller. Each processor module detects coherent transactions issued on the bus and performs cache coherency checks for each of the coherent transactions. Each processor module has a coherency queue for storing all transactions issued on the bus and for performing coherency checks for the transactions in first-in, first-out order. When a module transmits a coherent transaction on a bus, it places its own transaction into its own coherency queue.
89 citations
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IBM1
TL;DR: In this paper, a bridge circuit is proposed for coupling the first bus to the second bus to determine whether the address signal emitted by the processor corresponds to a peripheral device coupled to a bus subordinate to the bridge circuit.
Abstract: An information processing system comprises a processor, a first bus for conducting signals in accordance with a first bus protocol that does not support I/O address signals; a second bus for conducting signals in accordance with a second bus protocol that supports input/output (I/O) address signals; and a bridge circuit for coupling the first bus to the second bus. The processor includes a circuit for emitting address signals and an address type signal directed to a selected peripheral device. The bridge circuit comprises a filter for determining whether the address signal emitted by the processor corresponds to a peripheral device coupled to a bus subordinate to the bridge circuit; and a translation circuit, coupled to the filter, for translating signals in accordance with the first bus protocol to signals in accordance with the second bus protocol for transmission to the selected peripheral device.
88 citations
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TL;DR: The impact on transit ridership during the lockdown process was more significant than that on general traffic, and in the new normal situation, the general traffic and the shared bike system recovered a higher percentage of their previous use than the bus system.
Abstract: The COVID–19 pandemic led to restrictions on activities and mobility in many parts of the world. After the main peak of the crisis, restrictions were gradually removed, returning to a new normal situation. This process has impacted urban mobility. The limited information on the new normal situation shows changes that can be permanent or reversible. The impact on the diverse urban transport modes varies. This study analyzes the changes in transit ridership by line, the use of stops, the main origin–destination flows, changes in transit supply, operation time, and reliability of the city bus network of A Coruna. It is based on data from automatic vehicle location, bus stop boarding, and smart card use. Data from the first half of 2020 were compared to similar data in 2017–2019, defining suitable baselines for each analysis to avoid seasonal and day of week effects. The impact on transit ridership during the lockdown process was more significant than that on general traffic. In the new normal situation, the general traffic and the shared bike system recovered a higher percentage of their previous use than the bus system. These impacts are not uniform across the bus network.
88 citations
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29 Oct 1986
TL;DR: In this article, a bus device is provided for use in a data processing system which includes a plurality of bus devices interconnected by a synchronous bus, where the bus includes multiplexed data/address/arbitration lines which carry data, address and arbitration information during respective data, command/address, and arbitration cycles.
Abstract: A bus device is provided for use in a data processing system which includes a plurality of bus devices interconnected by a synchronous bus. The bus includes multiplexed data/address/arbitration lines which carry data, address, and arbitration information during respective data, command/address, and arbitration cycles. The bus also includes a BUSY line and a NO ARB line for controlling access to the data/address/arbitration lines. Where constructed as a memory device, the bus device includes memory circuits having a plurality of storage locations, and an interconnecting circuit which monitors the BUSY and NO ARB lines to identify various types of cycles on the bus, and which controls transmission of signals from the memory device over the bus in accordance with information derived by the monitoring means from the BUSY and NO ARB lines.
88 citations