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Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.


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Patent
10 May 1995
TL;DR: In this article, a message passing paradigm for transferring large amounts of input/output data among a plurality of processors, such as a network intermediate system or router, is used, where a bus interconnects the plurality of processor with a pluralityof bus interface devices, including a command list storing lists of commands which characterize transfers of data messages across the bus and a packing buffer which buffers the data subject of the command being executed between local memory and the bus.
Abstract: A system uses a message passing paradigm for transferring large amounts of input/output data among a plurality of processors, such as a network intermediate system or router. A bus interconnects the plurality of processors with a plurality of bus interface devices. The bus interface device which originates a transfer includes a command list storing lists of commands which characterize transfers of data messages from local memory across the bus and a packing buffer which buffers the data subject of the command being executed between local memory and the bus. A bus interface device which receives a transfer includes a free buffer list storing pointers to free buffers in local memory into which the data may be loaded from the bus, and a receive list storing pointers to buffers in local memory loaded with data from the bus. The command list includes a first high priority command list and a second lower priority command list for managing latency of the higher priority commands in the software of the processor. The bus interface which receives the transfer includes control logic which manages data transfer into and out of an inbound buffer, including receiving burst transfers of message transfer cells from the bus, loading free buffers in local memory from the inbound buffer with message transtar cells, and updating the receive list. The receive list includes a first higher priority receive list and a second lower priority receive list for reliability management, and logic which monitors the free list so that lower priority messages may be dropped to prevent overflow of free buffer resources.

206 citations

Journal ArticleDOI
TL;DR: The results show that the metro network resilience to disruptions can be enhanced significantly from localized integration with public bus services, and this approach is applied to a case study based on the Singapore public transit system and actual travel demand data.
Abstract: This paper advances the field of network disruption analysis by introducing an application to a multi-modal transport network, capitalizing on the redundancies and improved connectivity of an integrated metro-bus network. Metro network resilience to disruptions can be enhanced by leveraging on public bus services. To ensure better acceptance among operators and commuters, we focus on introducing localized integration with bus services instead of designing an entirely new bus network to achieve the desired resilience to potential disruptions. This is accomplished by increasing the capacity of bus services that run in parallel with affected metro lines as well as those connecting to different metro lines. Our analysis starts with a network representation to model the integrated metro and bus system. A two-stage stochastic programming model is further developed to assess the intrinsic metro network resilience as well as to optimize the localized integration with bus services. The approach is applied to a case study based on the Singapore public transit system and actual travel demand data. The results show that the metro network resilience to disruptions can be enhanced significantly from localized integration with public bus services.

202 citations

Journal ArticleDOI
TL;DR: By proving that the timetabling problem of Monterrey, Mexico is NP-hard, this work answers a 10-year-old open question about the NP- hardness of similar problems present in literature.
Abstract: Timetable generation is a subproblem of bus network strategic planning, in which the departure time of each trip is determined. We study the bus network of Monterrey, Mexico, which is similar to those of other cities in Latin America. It is a large bus network where passenger transfers must be favored, almost evenly spaced departures are sought, and bus bunching of different lines must be avoided. We formulate the timetabling problem of this network with the objective of maximizing the number of synchronizations to facilitate passenger transfers and avoid bus bunching along the network. We define these synchronizations as the arrivals of two trips with a separation time within a time window to make a flexible formulation. This flexibility is a critical aspect for the bus network, since travel times vary because of reasons such as driver speed, traffic congestion, and accidents. By proving that our problem is NP-hard we answer a 10-year-old open question about the NP-hardness of similar problems present in literature. Next, we analyze the structural properties of the feasible solution space of our model. This analysis leads to a preprocessing stage that eliminates numerous decision variables and constraints. Moreover, this preprocessing defines feasible synchronization and arrival time windows that are used in a new metaheuristic algorithm. Empirical experimentation shows that our proposed algorithm obtains high-quality solutions for real-size instances in less than one minute.

201 citations

Patent
30 Jun 1992
TL;DR: In this article, an arbitration system for a shared address, data and control bus provides burst mode operations for transferring data between a peripheral device and memory via a bus master, which is responsive to high priority bus activities such as memory refresh cycles and DMA cycles to temporarily transfer control of the shared bus from the bus master to a circuit controlling the high priority activity.
Abstract: An arbitration system for a shared address, data and control bus provides burst mode operations for transferring data between a peripheral device and memory via a bus master. The arbitration system is responsive to high priority bus activities, such as memory refresh cycles and DMA cycles to temporarily transfer control of the shared bus from the bus master to a circuit controlling the high priority activity. After the high priority activity is completed, the arbitration system returns control of the shared bus to the bus master so that the associated peripheral device may continue operating in the burst mode. This transfer of control occurs without requiring the time overhead of arbitrating priority between bus masters having active bus requests. The arbitration system further includes timing circuits to assure that a bus master transferring data in the burst mode does not retain control of the shared bus for an excessive amount of time.

200 citations

Journal ArticleDOI
TL;DR: A new method to compute fitness function (ff) values in genetic algorithms for bus network optimization by means of a multicriteria analysis executed on the performance indicators obtained by the analysis of the assignment of the O/D demand associated to the considered networks.
Abstract: This paper focuses on a new method to compute fitness function (ff) values in genetic algorithms for bus network optimization. In the proposed methodology, a genetic algorithm is used to generate iteratively new populations (sets of bus networks). Each member of the population is evaluated by computing a number of performance indicators obtained by the analysis of the assignment of the O/D demand associated to the considered networks. Thus, ff values are computed by means of a multicriteria analysis executed on the performance indicators so found. The goal is to design a heuristic that allows to achieve the best bus network satisfying both the demand and the offer of transport.

199 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202229
202192
202093
201999
2018108