Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.

Apparatus and method for a synchronous, high speed, packet-switched bus

Abstract: A high speed, synchronous, packet-switched inter-chip bus apparatus and method for transferring data between multiple system buses and a cache controller. In the preferred embodiment, the bus connects a cache controller client within the external cache of a processor to a plurality of bus watcher clients, each of which is coupled to a separate system bus. The bus allows the cache controller to provide independent processor-side access to the cache and allows the bus watchers to handle functions related to bus-snooping. An arbiter is employed to allow the bus to be multiplexed between the bus watchers and cache controller . Flow control mechanisms are also employed to ensure that queues receiving packets or arbitration requests over the bus never overflow. A default grantee mechanism is employed to minimize the arbitration latency due to a request for the bus when the bus is idle.

A bus on a diet-the serial bus alternative-an introduction to the P1394 High Performance Serial Bus

Abstract: The author discusses the justifications for the use of a serial bus in computer systems. He then describes a leading proposal for such an interconnect: the IEEE P1394 High Performance Serial Bus. The highlights of the Serial Bus include: (1) a physical layer supporting both cable media and many ANSI/IEEE standard 32-bit buses; (2) variable speed data transmission with a base speed of almost 100 Mbit/sec between nodes separated by distances up to 10 meters; (3) both fair and priority arbitration mechanisms with all nodes guaranteed at least partial access to the bus regardless of priority; (4) bus transactions that include block and single quadlet reads and writes, as well as an isochronous mode which provides a low-overhead guaranteed bandwidth service; and (5) dynamic address assignment that does not require switches or a physical 'slot number'. >

Dual bus communication system

Abstract: A dual set of busses is used to provide close coupling between the data and voice services of the CS300 communication system. One of these busses is a time division multiplex bus arranged for communication between port access circuits, and the other bus is a packet-switched data processing bus used for interfacing both with the system peripherals and with the port access circuits. The port access circuits, as well as the faster peripheral circuits, can be connected to either or both busses thereby allowing for the efficient easy interchange of information.

Arrayed data storage architecture with simultaneous command of multiple storage media

Abstract: A storage system controller (302) includes a plurality of media controllers (301), a local microprocessor (306), and a host interface logic (310), operably coupled by a multi-drop parallel bus. The multi-drop parallel bus (319) includes a control bus (324), a payload data bus (320), a real-time ready-status (data ready) signaling bus (322) and a general microprocessor bus (330). Each media controller has a storage media (311) operably coupled thereto. Each media controller includes a parameter storage (404), a media interface circuit (406), a control data state machine (408), a command sequencer state machine (410), a media-side multi-mode transfer state machine (412), a dual-port memory (402), a memory controller (420), and a host-side transfer state machine (430). The host interface logic and the media controllers are implemented in one or more Field Programmable Gate Arrays. The storage system architecture allows the microprocessor to simultaneously broadcast a command to the media controllers, which have a capability to substantially simultaneously begin exchanging data with the storage media in response to the command. The storage system has provision for Redundant Array of Independent Disks, method 0, operation.

Backup control mechanism in a distributed control network

Abstract: A multi-tier, master-slave control network having redundant backup for a master node in which the slave nodes are provided with means for detecting a failure of the master node and for taking over for the master node in such circumstances. The master node and slave nodes are connected to a common bus. Each of the slave nodes has an uplink transceiver and a downlink transceiver, with the downlink transceiver ordinarily isolated by switches from the common bus. Each of the slave nodes has a timer programmed with a separate failure mode detection time period. When a slave mode fails to receive control messages from the master node for a period exceeding its programmed failure mode detection time period, the slave node takes over for the master node. Because each slave node has a separate failure mode detection time period, a priority is established in which the slave nodes will take over for the master node, and redundant master backup control is provided. A preferred embodiment of the control network has multiple buses, one bus for each tier, and each bus has a master node and a plurality of slave nodes, with each of the slave nodes capable of taking over for the master node on the slave node's particular bus.