Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.

Apparatus and method for entering low power mode in a computer system

Abstract: A power management circuit for managing low power modes in a computer system, which implements four power modes, from highest power consumption to lowest power consumption: RUN mode, SLEEP mode, IDLE mode, and STANDBY mode. The computer system includes a PCI bus and an ISA bus, with a CPU-PCI bridge to connect the host bus and the PCI bus and a PCI-ISA bridge to connect the PCI bus and the ISA bus. The power management circuit transitions from SLEEP mode to IDLE mode by first determining if the CPU-PCI bridge is parked on the PCI bus and if it is in SLEEP mode. The power management circuit then waits for one refresh period and for all internal queues to empty before checking again to determine if the CPU-PCI bridge is still parked on the PCI bus and if it is still in SLEEP mode. If true, the CPU-PCI bridge transitions to IDLE mode. The power management circuit also performs low power refresh cycles when it is in IDLE or STANDBY mode. In those modes, the memory controller in the CPU-PCI bridge is disabled to conserve power. The power management circuit performs the refresh cycles based off an external asynchronous clock. Further, the power management circuit drives certain PCI bus signals to a certain state to avoid leakage current due to the existence of a mixture of 3.3-volt and 5-volt components connected to the PCI bus.

Digital data processor apparatus with pipelined fault tolerant bus protocol

Abstract: A fault-tolerant computer system provides information transfers between the units of a computing module, including a processor unit and a memory unit and one or more peripheral control units, on a bus structure common to all the units. Information-handling parts of the system, both in the bus structure and in each unit, can have a duplicate partner. Error detectors check the operation of the bus structure and of each system unit to provide information transfers only on fault-free bus conductors and between fault-free units. The computer system can operate in this manner essentially without interruption in the event of faults by using only fault-free conductors and functional units. Arbitration circuits of unusual speed and simplicity provide units of the computing module with access to the common bus structure according to the priority of each unit. The units of a module check incoming and outgoing signals for errors, signal other module units of a detected error, and disable the unit from sending potentially erroneous information onto the bus structure.

Function-distributed control apparatus

Abstract: A function-distributed control apparatus comprises a first bus, a second bus, and at least one base processor element which includes a first main processing unit connected to at least the first bus, a second main processing unit connected to at least the second bus, and a dual-port memory with a mutual interrupt circuit connected to both these main processing units for communications between them. The first bus and the first main processing unit are chiefly for intelligent processing required for controlling a machine, while the second bus and the second main processing unit are chiefly for motion control of the machine. Those buses are also connected to various intelligent subsystems each including a processing unit and a dual-port memory with a mutual interrupt circuit for communications with the base processor element.

Network controller for digitally controlling remote devices via a common bus

Abstract: The present invention provides a network controller that directs communications with a variety of remote devices via a common bus. The network controller includes a transmitter for transmitting messages via the common bus, and a receiver for receiving messages from the common bus. Additionally, the network controller includes a clock for providing clock signals to both the transmitter and receiver. The transmitter and receiver are selected such that the network controller is capable of selectively operating in either synchronous or asynchronous mode. In operation, the network controller is configured in either a Manchester encoding or a Universal Asynchronous Receiver Transmitter (UART) protocol. The transmitter transmits messages comprising a command and an address of at least one remote device. In one embodiment, the transmitter simultaneously transmits messages to a plurality of remote devices in accordance with a group address comprised of a multiple bits with each bit associated with a respective group.

Staged partitioned communication bus for a multi-port bridge for a local area network

Abstract: A staged partitioned communication bus for interconnecting the ports of a multi-port bridge for a local area network. The communication bus is partitioned into a plurality of data bus segments. Each data bus segment is coupled to one or more ports of the multi-port bridge and includes a same number of signal lines. A multiplexer is coupled to each data bus segment and to a memory device. A bus controller is coupled to each port and to the multiplexer. Each port requests access to the memory device from the bus controller for storing packets in the memory device and for retrieving packets therefrom. In response, the bus controller conditions the multiplexer to provide a signal path between the memory device to and the data bus segment which includes the requesting port. The memory device temporarily stores packets undergoing communication between the ports. Accordingly, a source port for a packet transfers the packet to the memory device via the multiplexer and, then, a destination port for the packet retrieves the packet from the memory device via the multiplexer. If the source port and the destination port are on a same data bus segment and the destination port is not currently busy, the destination port receives the packet directly from the source port as the source port stores the packet in the memory device. A look-up bus can be included, which is operable independently of the staged partitioned bus, for correlating destination addresses for packets to identifications of destination ports.