Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.

Single instruction multiple data (SIMD) cellular array processing apparatus employing a common bus where a first number of bits manifest a first bus portion and a second number of bits manifest a second bus portion

Abstract: In a cellular array including a matrixed array of processing elements, the processing elements are controlled by software to overcome manufacturing defects, to cooperate together to form words of varying size and to replace cells that become defective during the lifetime of the processor. These cells communicate with memory external to the chip via a time division multiplex bus. The bus is 32-bits wide and each cell is connected to both the upper half and the lower half of the bus. Configuration bits that are loaded into a cell cause communication over the top half or the bottom half of the bus according to the significance of the bits placed in the cells. Words between 16-bits and 246-bits in length may be formed in a case where 20 such cells are implemented on a single chip with four of the cells being deemed to be spare parts. For simplicity, typical word sizes would be 2n×16 bits although in principle any multiple of 16-bits may be obtained. Each cell contains a 16-bit multiport RAM providing general purpose registers for use by the programmer as well as systems registers. The systems registers accommodate the processor status word, a multiplier quotient register, a full-function arithmetic logic unit and path logic to connect the cells together and control the flow of information through the path logic according to the instruction being executed.

Method and system for supporting multiple bus protocols on a set of wirelines

Abstract: A universal bus communicates information by one of plural bus protocols. A bus protocol selector is operable to select one of the plural bus protocols associated with a device interfaced with an information handling system and to communicate information over the bus with the selected bus protocol. An Input/Output chip includes a protocol selector unit that selects a bus protocol I/O unit to communicate with the device over the universal bus. The bus protocol I/O unit communicates over the universal bus by using a bus protocol that is compatible with the device. For instance, the one of plural available differential serial bus protocols is selected so that the bus protocol I/O unit communicates with the device using a bus protocol compatible with the device. In some instances, a bypass circuit configures the physical characteristics of the universal bus, such as by interfacing or removing a capacitor with the universal bus to support AC or DC coupled bus protocols.

Computer system with a processor-direct universal bus connector and interchangeable bus translator

Abstract: A universal processor-direct bus structure on a specifically partitioned motherboard uses a separate local bus translator card to adapt to a specific local bus protocol and configuration The processor-direct bus on the motherboard contains a superset of all of the primary signals required to implement any desired local bus structure The translator card incorporates the connectors and bus translation protocol for a specific local bus structure on a separate card which is connected to the partitioned motherboard through the universal processor-direct bus Thus, the universal processor-direct bus combined with the translator card makes it possible to have a standard bus (for example an ISA (Industry Standard Architecture) bus, EISA bus, MCA bus, PCI bus, C-bus, S-100 bus and/or other buses) mounted directly on the motherboard with one or more of the same standard buses or a different local bus interfaced to the motherboard through the universal processor-direct bus This unique combination of a motherboard having a universal processor-direct bus with plug in local bus translator cards provides a unique, low cost, flexible solution to the problem of standard and local bus obsolescence, local bus non-upgradeability and local bus non-flexibility

Reconfigurable data bus

Abstract: A digital data communication system having a plurality of digital nodal communication devices interconnected by a digital data bus in a fixed physical manner in which the data bus structure may be electrically reconfigured without physical modification of the digital data bus. The ability to reconfigure the digital data bus is accomplished by the insertion of a digital reconfigurable data bus module into the position on the digital data bus previously held by one of the digital nodal communication devices and the connection of the replaced digital nodal communication device to the digital reconfigurable data bus module. The digital reconfigurable data bus module contains a transceiver mechanism capable of receiving and transmitting digital information to and from the digital data bus, an adapter mechanism for communicating with the replaced digital nodal communication device and a switching mechanism capable of the multiple switching of data from the adapter section which is connected to the replaced digital nodal communication device to the transceiver section which is connected to the digital data bus. The digital reconfigurable data bus module allows a fixed configuration of nodal devices and connecting devices to provide the function of tree structured buses, ring structured buses, dedicated channels or combinations of any of them. The module facilitates the receipt, switching and retransmission of data on any selected bus pattern.

Data routing using status-response signals

Abstract: A method and apparatus for routing data between bus devices, where each bus device is connected to a centralized switch via a point-to-point bus connection. The plurality of point-to-point bus connections collectively form a system bus. After a command is issued on the system bus, each bus device responds to the issued command by transmitting an address status response to a response combining logic module. The response combining logic module identifies which of the bus devices responded with a positive acknowledgment to the issued command, then forwards a device identifier of the bus device responding with the positive acknowledgment to the switch. The switch uses the device identifier returned via the response combining logic to route the data transfer associated with the issued command.