Topic
Bus network
About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.
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Patent•
IBM1
TL;DR: In this paper, a switching network interconnects several multi-drop buses using adapters to connect the buses to the switching network, and the adapters implement hardware functions to appear to software as if all devices on the several buses were attached to a single large bus.
Abstract: An electronic switching and data transmission system for interconnecting a plurality of buses. A switching network interconnects several multi-drop buses using adapters to connect the buses to the switching network. The adapters implements hardware functions to appear to software as if all devices on the several buses were attached to a single large bus. The system permits higher speed transfer modes by eliminating multi-drop bus limitations.
71 citations
Patent•
20 Nov 1998TL;DR: In this article, the IEEE 1394 serial bus, during bus initialization, transmits a plurality of self-ID packets across the bus, which are stored in a FIFO for later use by a host interface.
Abstract: An IEEE 1394 serial bus, during bus initialization, transmits a plurality of self-ID packets across the bus. Each node on the bus is operable to receive the self-ID packet from the bus (140) via receiver (146). Asynchronous packets and isochronous packets are stored in a FIFO (166) for later use by a host interface (150). The self-ID packets are verified by a hardware circuit (170) that provides verification of the self-ID packets as they are received without requiring the software to later evaluate the self-ID packets from storage in the FIFO (166). If an error is determined, this is stored in registers (164) for later processing by the host interface (150).
71 citations
TL;DR: In this paper, the performance of four passive optical network topologies in implementing multi-user quantum key distribution is compared, and an analysis of the quantum bit-error rate and sifted key rate for each of these topologies is used to determine their suitability for providing service to networks of various sizes.
Abstract: The performance of four passive optical network topologies in implementing multi-user quantum key distribution is compared. The networks considered are the passive-star network, the optical-ring network based on the Sagnac interferometer, the wavelength-routed network, and the wavelength-addressed bus network. An analysis of the quantum bit-error rate and sifted key rate for each of these topologies is used to determine their suitability for providing service to networks of various sizes.
71 citations
Patent•
04 Jun 1991
TL;DR: A matrix processor as discussed by the authors is a system with a variable number of buses, each bus having a variable-number of processing elements which may operate in parallel and can be configured as a coprocessor or as a stand-alone device.
Abstract: A matrix processor comprises a system with a variable number of buses, each bus having a variable number of processing elements which may operate in parallel. Each bus accesses a port into a memory crossbar and a multiport memory system also accesses crossbar ports. Efficient sharing of bus accesses by processors and synchronization of processors on each bus is accomplished via registers located on the buses, which may be read and written by processors. Interbus synchronization is also accomplished via register accesses. The matrix processor may be configured as a coprocessor or as a stand alone device. A method of synchronizing the processors and buses, performed by at least one processor on at least one bus, includes reading a barrier state of the processors, synchronizing the processing elements on a each bus, reading the barrier state of the buses, and synchronizing each bus.
71 citations
Patent•
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TL;DR: In this paper, a radio frequency (RF) bus controller includes an interface and a processing module, coupled for communicating intra-device RF bus access requests and allocations, and when sufficient RF bus resources are available, allocate, via the interface, at least one RF bus resource in response to the access request.
Abstract: A radio frequency (RF) bus controller includes an interface and a processing module. The interface is coupled for communicating intra-device RF bus access requests and allocations. The processing module is coupled to receive an access request to an RF bus via the interface; determine RF bus resource availability; and when sufficient RF bus resources are available to fulfill the access request, allocate, via the interface, at least one RF bus resource in response to the access request.
70 citations