Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.

Network switch including a switch manager for periodically polling the network ports to determine their status and controlling the flow of data between ports

Abstract: A network switch including one or more network ports for receiving and transmitting data is disclosed. The network switch also includes a processor, a switch manager, and memory. Each port includes a network interface, a data bus interface, and a processor port interface. A data bus is coupled to the data bus interface of each of the ports and the switch manager. A processor bus is coupled to a processor, the switch manager, and to the processor port interface of each of the ports. A memory bus is coupled to the memory and the switch manager. The switch manager periodically polls each of the network ports to determine the status of each port. The switch manager controls the flow of data between the network ports and memory based on the port status. The separate processor bus allows the processor to perform overhead functions, such as monitoring, determining status and configuration, without consuming valuable data bus bandwidth.

System for reformatting a response packet with speed code from a source packet using DMA engine to retrieve count field and address from source packet

Abstract: A high performance serial bus operating at multiple transmission rates is disclosed. The serial bus is able to automatically generate data response packets for return to a requesting node. The automatic packet generation uses the source and destination information to generate a return destination packet for directing the requested data to the request source destination. Since the bus network is capable of operating at several different transmission rates, the speed at which the data request packet was transmitted is used for retransmitting the data requested back to the source node requesting the data.

System bus for an emulated multichannel system

Abstract: A single synchronous system bus interconnecting a number of distributed processors which emulate multiple channels of a multichannel system. The system uses multichannel software and each channel is distributed among all of the distributed processors. The bus provides for communication among the distributed processors and a memory controller. One of the distributed processors accepts and converts multichannel software and transmits formatted words on the system bus and another of the distributed processor stores the instruction received in the formatted words. The first processor, thereby, acquires control over the system bus and the second processor, as slave, processes the instruction received in accordance with its microde programming, generates data transfer control signals and transmits formatted words via the system bus destined for a distributed processor or main memory controller. The processor which transmitted the formatted words to a destination device relinquishes control of the system bus and the destination device acquires control of the system bus for processing the words transmitted to it.

Split computer architecture to separate user and processor while retaining original user interface

Abstract: A network interface is described in which a single computer bus is split over a long distance into two or more inter-communicating buses. On one bus, processing and applications are provided and on the other remote bus, peripheral and local controllers are provided. The buses communicate through a series of: bridge, FPGA, FPGA and bridge. Between the FPGAs, a communication path provides long distance communication.