Topic
Bus network
About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.
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20 Apr 2010
TL;DR: In this article, a closed-grid bus is used to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channels can concurrently communicate with all of the I/O pads.
Abstract: An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect structure includes a circuit board implementing an array of bus nodes, each corresponding to a separate one of the I/O pads. The circuit board includes at least two layers. Traces mounted on a first layer form a set of first daisy-chain buses, each linking all bus nodes of a separate row of the bus node array. Traces mounted on a second circuit board layer form a set of second daisy-chain buses, each linking all bus nodes of a separate column of the bus node array. Vias and other circuit board interconnect ends of the first and second daisy-chain buses so that they form the closed-grid bus. Each bus node is connected though a separate isolation resistor to a separate contact pad mounted on a surface of the circuit board. A set of spring contacts or probes link each contact pad to a separate one of the I/O pads on the wafer.
69 citations
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IBM1
TL;DR: In this paper, the authors propose an approach for assigning addresses to devices connected to an SCSI bus, where the master device transmits configuration commands over the configuration bus and addresses for assignment over the SCSI Bus.
Abstract: Apparatus for assigning addresses to devices connected to an SCSI bus (10). A second configure bus (15) interconnects address assignable devices on the SCSI bus. The assignable devices may be used in a mixed system where some devices have fixed non-assignable addresses. The master device in the SCSI bus transmits configuration commands over the configuration bus and addresses for assignment over the SCSI bus. Acknowledgements are received back from a device which has accepted an address. Once configured with an address, the device propagates subsequent configuration commands to an adjacent device.
69 citations
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21 May 1998
TL;DR: In this paper, bus arrangements for interconnecting a number of discrete and/or integrated modules in a digital system are discussed, where the bus arrangement is capable of supporting more active transactions than the number of individual buses (50, 52, 54).
Abstract: Bus arrangements for interconnecting a number of discrete and/or integrated modules in a digital system (10) are disclosed herein. Implementations of the bus arrangements are contemplated at chip level, forming part of an overall integrated circuit, and are also contemplated as interconnecting discrete modules within an overall processing system (10). These bus arrangements and associated method provide for high speed, efficient digital data transfer between the modules through optimizing bus utilization by eliminating the need for maintaining a fixed time relationship between the address and data portions of transactions which are executed by the system (10). In this manner, the bus arrangement is capable of supporting more active transactions than the number of individual buses (50, 52, 54) which make up the bus arrangement. Systems (10) disclosed may include any number of individual buses within their bus arrangements. In one implementation, a system includes a single address bus (50) and two or more data buses (52, 54) such that different data transfers may be executed simultaneously on each data bus.
68 citations
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IBM1
TL;DR: In this paper, the authors present an approach and method for enabling asynchronous, collision-free communication between ports on a local shared bus network which is efficient in the use of bus bandwidth and which, in one embodiment, provides a bounded, guaranteed time to transmission for each port.
Abstract: Apparatus and method for enabling asynchronous, collision-free communication between ports on a local shared bus network which is efficient in the use of bus bandwidth and which, in one embodiment, provides a bounded, guaranteed time to transmission for each port.
68 citations
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02 Oct 1992
TL;DR: In this paper, the authors propose a method and apparatus for concurrent operations on the host bus, expansion bus, and local I/O bus as well as the processor bus connecting the processor and cache system to increase computer system efficiency.
Abstract: A method and apparatus for performing concurrent operations on the host bus, expansion bus, and local I/O bus as well as the processor bus connecting the processor and cache system to increase computer system efficiency. A plurality of CPU boards are coupled to a host bus which in turn is coupled to an expansion bus through a bus controller. Each CPU board includes a processor connected to a cache system including a cache controller and cache memory. The cache system interfaces to the host bus through address and data buffers controlled by cache interface logic. Distributed system peripheral (DSP) logic comprising various ports, timers, and interrupt controller logic is coupled to the cache system, data buffers, and cache interface logic by a local I/O bus. The computer system supports various areas of concurrent operation, including concurrent local I/O cycles, host bus snoop cycles and CPU requests, as well as concurrent expansion bus reads with snooped host bus cycles.
68 citations