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Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.


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Patent
07 Sep 1994
TL;DR: In this paper, a computing system, having an input/output bus for communicating data thereon, is connected to a network by a pair of network controller devices, in turn, connect to a corresponding one of the multi-ported network repeater elements which are connected to one another by a network link, and if receipt of those messages by the primary network controller is noted, the selection of the primary controller will be switched to another.
Abstract: A computing system, having an input/output bus for communicating data thereon, is connected to a network by a pair of network controller devices. Each of the network controller devices, in turn, connect to a corresponding one of a pair of multi-ported network repeater elements which are, in turn, connected to one another by a pair of network links. At least one workstation is connected to each of the network repeaters. One of the network controllers is initially selected as a primary data communicating path from the computing system to the network. The network controllers periodically transmit messages to one another, and if receipt of those messages by the primary network controller is noted, the selection of the primary controller will be switched to the other.

67 citations

Journal ArticleDOI
TL;DR: A new class of interconnection network topology is proposed for parallel and distributed processing that can be constructed for any number of computing nodes and has good fault-tolerant characteristics.
Abstract: A new class of interconnection network topology is proposed for parallel and distributed processing. The attractive features of this class include (a) the network can be constructed for any number of computing nodes, (b) the network is incrementally expandable, i.e., a new node can easily be added to the existing network, (c) it has good fault-tolerant characteristics (measured by the connectivity of the network graph) and (d) it has small delay characteristics (measured by the diameter of the network graph). The node connectivity of the network is equal to the minimum node degree. In this sense the network is optimally fault-tolerant.

67 citations

Patent
William S. Duckwall1
01 Dec 1995
TL;DR: In this paper, an electronic system comprises a plurality of components each having at least one communication node and being coupled together by communication links through the respective communication nodes so that the plurality of communication links and communication nodes form a bus which resembles an acyclic directed graph having established hierarchical parent-child relationships between adjacent nodes and a root node.
Abstract: An electronic system comprises a plurality of components each having at least one communication node and being coupled together by communication links through the respective communication nodes so that the plurality of communication links and communication nodes form a bus which resembles an acyclic directed graph having established hierarchical parent-child relationships between adjacent nodes and a root node. Token passing style arbitration is implemented on the system, in one embodiment, in response to the root node sending out an unrequested bus grant, so that the node with the token has access to the bus.

67 citations

Patent
16 May 1997
TL;DR: In this paper, the authors present a real-time application optimized for realtime applications which provides increased performance over current computer architectures, including a standard local system bus or expansion bus, such as the PCI bus, and also includes a dedicated real time bus or multimedia bus, which operates to direct or pull stream information through the system.
Abstract: A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus or expansion bus, such as the PCI bus, and also includes a dedicated real-time bus or multimedia bus. Various multimedia devices are coupled to one or more of the expansion bus and/or the multimedia bus. The computer system includes a dedicated or centralized I/O processor coupled to one or more of the expansion bus and/or the multimedia bus which operates to direct or pull stream information through the system. The centralized I/O processor comprises a memory for storing data rate, data periodicity, data source, and data destination information for said multimedia devices. The computer system of the present invention thus provides much greater performance for real-time applications than prior systems.

67 citations

Patent
31 Mar 1998
TL;DR: In this article, a host bridge is employed to issue deferred transactions over the P6 bus without interrupting or involving the main processor, and a handshake with a host master and issuing a request over the host bus.
Abstract: A method of communication between requester and target devices in a computer system having a multiple bus architecture. The method supports deferred transactions of cache line read requests over a host bus, e.g., the Pentium II or Pentium Pro (P6) bus. The method employs a host bridge to issue deferred transactions over the P6 bus without interrupting or involving the main processor. The method comprises the act of establishing a handshake with a host master and issuing a request over the host bus. The method further comprises the act of acknowledging the request and transmitting a deferred response to the requester.

67 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202229
202192
202093
201999
2018108