Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.

Single conductor multi-frequency electric wiring system for vehicles

Abstract: A wiring system for use in vehicles wherein a common single conductor bus is utilized for both power and control function transmission. A plurality of transmitters attached to the bus receive power from the bus and supply control signals to the bus as required. A plurality of receivers, attached to the bus, receive power and the control signals from the bus. Each receiver is tuned to respond only to the particular control signal produced by a single transmitter. Upon receipt of the appropriate control signals, the receivers couple power from the bus to various loads.

The Concept of Betweenness in the Analysis of Power Grid Vulnerability

Abstract: Vulnerability analysis in power systems is a key issue in modern society and many efforts have contributed to the analysis. Recently, complex network metrics applied to assess the topological vulnerability of networked systems have been used in power systems, such as betweenness metric, since transmission of power systems is in basis of a network structure. However, a pure topological approach fails to capture the specificity of power systems. This paper redefines, starting from the concept of complex networks, an electrical betweenness metric which considers several of specific features of power systems such as power transfer distribution and line flow limits. The electrical betweenness is compared with the conventional betweenness in IEEE-300 bus network according to the un-served energy after network is attacked. The results show that the tested network is more vulnerable when the components of the network are attacked according to their criticalities ranked by electrical betweenness.

An active star topology for improving fault confinement in CAN networks

Abstract: The controller area network (CAN) is a field bus that is nowadays widespread in distributed embedded systems due to its electrical robustness, low price, and deterministic access delay. However, its use in safety-critical applications has been controversial due to dependability limitations, such as those arising from its bus topology. In particular, in a CAN bus, there are multiple components such that if any of them is faulty, a general failure of the communication system may happen. In this paper, we propose a design for an active star topology called CANcentrate. Our design solves the limitations indicated above by means of an active hub, which prevents error propagation from any of its ports to the others. Due to the specific characteristics of this hub, CANcentrate is fully compatible with existing CAN controllers. This paper compares bus and star topologies, analyzes related work, describes the CANcentrate basics, paying special attention to the mechanisms used for detecting faulty ports, and finally describes the implementation and test of a CANcentrate prototype.

Masterless and contentionless computer network

Abstract: A computer network is disclosed in which a plurality of computer stations are interconnected by a single bus and wherein access to the bus is controlled by the computer stations themselves through an adapter unit at each station. Each adapter unit is assigned a unique number. When the network is running normally, control of the bus is continually passed from one live adapter unit to another in numerical sequence and the bus is active with messages, control signals or status signals from the particular adapter unit that happens to be in control at the time. If, for any reason, there should be no activity on the bus for a preselected time interval, all adapter units detecting this condition enter an election mode to elect from amongst themselves one adapter unit to assume control and resume activity. In the election mode, each participating adapter unit sends a pulse out over the bus and then monitors the bus for activity for a time period directly proportional to its assigned number. The first adapter unit whose time period expires without detecting activity is the winner and sends another pulse out over the bus causing the other participating adapter units to detect activity before their time periods expire and thus become losers in the election. Each adapter unit includes a line activity indicator for monitoring the bus for activity, a timer for measuring time, a switch which is used in generate pulses and circuitry for interfacing the computer at its associated station to the bus.

Synchronous bus arbiter

Abstract: Un dispositif d'arbitrage de bus pour resoudre le probleme des requetes en concurrence d'acces a un bus (3) est associe a des lignes locales de commande de signaux (19) qui sont couplees a son 'maitre' associe (c'est-a-dire l'utilisateur du bus 1-N), et a des lignes de commande (6) du bus communes a toutes les autres unites Ces lignes locales de commande de signaux (19) comprennent un ensemble de lignes d'identification (25) definissant l'adresse (et le rang de priorite) du maitre associe, une ligne de requete (22) par l'intermediaire de laquelle les requetes des maitres ont acces au bus, une ligne de concession (23) par l'intermediaire de laquelle un maitre est informe qu'il possede la commande du bus, et une ligne de liberation (24) par l'intermediaire de laquelle le maitre informe le circuit de commande d'echange du bus (20) qu'il libere sa commande du bus. A bus arbitration system to solve the problem of queries in Access competition has a bus (3) is associated with local loop signal control (19) that are coupled to its 'master' associates (that is -a say user 1-N bus) and control lines (6) of the bus common to all the other units These local lines signal control (19) comprise a set of identification lines ( 25) defining the address (and rank priority) combines the master, a line of application (22) through the intermediary of which the queries of teachers have access to the bus, a concession line (23) through the intermediary which a teacher is informed that he possesses control of the bus, and a line of liberation (24) through the intermediary of which the master informs the control circuit for refilling the bus (20) that he frees his order the bus. Des lignes de commande qui sont communes a d'autres unites sur le bus comprennent une ligne d'occupation (32), par laquelle chaque circuit d'interface est avise que le bus est actuellement en service, une ligne d'horloge de bus (34) pour la synchronisation du fonctionnement des circuits de commande d'echange de bus (20), un ensemble de lignes de demande du bus (33) par l'intermediaire desquelles les adresses des utilisateurs demandant le bus sont acheminees et par l'intermediaire desquelles le probleme de priorite entre des demandes en conflit est resolu, et une ligne d'accuse de reception de selection (31) qui est utilisee pour mettre fin a la resolution de priorite une fois qu'il a ete determine quel est l'utilisateur demandeur qui possede la priorite la plus grande. control lines that are common to other units on the bus include a busy line (32), through which each interface circuit is advised that the bus is currently in service, a bus clock line ( 34) for synchronizing the operation of the control circuits of bus exchange (20), a set of bus request lines (33) through which the addresses of users requesting the bus and are conveyed by the intermediary where the problem of priority between conflicting requests is resolved, and a line accuses selection of reception (31) which is used to put an end to the priority of resolution once it was determined what the user applicant who possesses the highest priority. Le circuit de commande d'echange de bus (20) contient lui-meme un ensemble de logiques de combinaison (fig. 3) qui effectue un ensemble de taches d'entretien domestiques en utilisant les lignes de signaux de commande (6) de maniere a permettre a son maitre associe (1-N) d'obtenir la commande du bus (3) lorsqu'il est requis et, dans l'eventualite d'une pluralite de demandes simultanees de The control circuit bus exchange (20) itself contains a set of logical combination (Fig. 3) which performs a set of household cleaning stains using control signal lines (6) so a permit to his master associates (1-N) to obtain control of the bus (3) where required and in the eventuality of a plurality of simultaneous requests