Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.

Openbus system for control automation networks

Abstract: A novel control automation system for enabling I/O boards to access communication networks for receiving and transmitting real time control information over a communication network is disclosed. The system includes a control bus, a node controller and a development system. External hardware that connects to I/O devices such as sensors, motors, monitors, machines, etc. can be connected to the invention via I/O boards that receives and transmit digital signals, representing control information, to the bus. The bus functions as the hub of operation, receiving network communications, processing cooperative logic and transmitting information over the communication network. The bus enables single or multiple controllers to access real time information generated by the attached hardware. The bus also enables the execution of I/O operations that originated in external controllers and transmitted over the communication network. The bus allows any I/O control board having a common interface, such as ISA, PCI, Compact PCI, etc., to connect to the bus by attachment to one of its slots. An intelligent embedded implementation process provides the logic necessary to enable the connectivity between the I/O boards and the communication network. The development system includes a real-time compiler for generating p-code to be executed on the real-time kernel running in the node controller. The real-time compiler generates p-code from the combination of event triggers, event actions and program logic making up the user's application.

High speed bus system

Abstract: In the high speed bus system of the present invention, the bus configuration is one in which all master devices are clustered at one end of an unterminated end of the bus. The slaves are located along the remaining length of the bus and the opposite end of the transmission line of the bus is terminated. By eliminating the termination resistor at the end of the bus where the master devices are located the required drive current needed to produce a given output swing is reduced. The bus drivers and receivers are CMOS integrated circuits. The bus of the present invention is operable utilizing small swing signals which enable sufficient implementation of current mode drivers for low impedance bus signals. In particular, the bus input receiver of the present invention comprises a two stage buffered sampler/amplifier which receives a small swing signal from the bus and samples and amplifies the low swing signal to a full swing signal within a single clock cycle using CMOS circuits.

A network switch with a multiple bus structure and a bridge interface for transferring network data between different buses

Abstract: A network switch includes a plurality of first network ports coupled to a first bus, a plurality of second network ports coupled to a second bus, a bridge interface enabling data transfer between the buses, a switch manager controlling the flow of network data, and a processor for performing supervisory and control functions. The first and second network ports operate according to different network protocols, and the first and second buses operate according to different bus standards. During packet data transfers across the first bus, the bridge interface emulates a first network port. During packet data transfers across the second bus, the bridge interface primarily acts as a slave to the second network ports by storing control lists for execution by the second network ports, thus relieving the processor of performing overhead functions associated with data transfers across the second bus.

Bus system optimization

Abstract: A bus system comprising a master connected to one or more slave devices via a bus is disclosed. The bus system is able to effectively communicate control information during a calibration phase and to individually determine appropriate timing and/or voltage offsets for each slave device. The offsets are used to optimise transfer timing (including duty cycle characteristics), signal equalization, and voltage levels for data exchanged between the master and the slave devices.