Topic
Bus network
About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.
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TL;DR: In this paper, the authors review the experience from the service upgrades to assess how effective they have been in terms of these agendas and suggest reasonable minimum service levels are required to attract new riders in times of modal shift, and are effective at building social capital.
61 citations
Patent•
08 Feb 1989
TL;DR: In this article, a hierarchical bus system interconnects the multicomputers so as to permit efficient routing of data between the various computers, and a complete wafer may be manufactured so that it contains many of the multi-computers.
Abstract: A multicomputer chip has a common bus and up to ten microcomputers connected in parallel to the common bus via routers contained in the microcomputers. The common bus can be connected to an external bus by means of a router mounted on or off the chip. Any defective computer found during testing can be rendered inactive by assigning it an unused address and, in this way, the remaining computers are unaffected. Instead of providing each multicomputer on a separate chip, a complete wafer may be manufactured so that it contains many of the multicomputers. A hierarchical bus system interconnects the multicomputers so as to permit efficient routing of data between the various computers.
61 citations
Patent•
18 Jun 1999
TL;DR: In this paper, a verification engine for verifying the design of a target system having a plurality of components interconnected by a number of target system buses is described. But the verification engine consists of a first hardware model and a second hardware model, both configured as a component and having a set of hardware model input/output pins.
Abstract: A verification engine for verifying the design of a target system having a plurality of components interconnected by a plurality of target system buses is disclosed. The verification engine comprises a first hardware model and a second hardware model, both configured as a component and having a set of hardware model input/output pins. In addition, a first bus wrapper is connected to the first hardware model and a second bus wrapper is connected to the second hardware model. Further, a set of bus lines are each connected to the first bus wrapper and the second bus wrapper. Each bus wrapper also has switchable communicative circuitry that switchably communicatively connects each hardware model input/output pin to a bus line and has a control block controlling the switchable communicative circuitry. A system controller is connected to at least some of the bus lines and is adapted to transmit a sequence of time synchronization information to each bus wrapper control block by way of the bus lines. Finally, responsive to a predetermined one of the time slot numbers both of the control blocks switch at least one input/output pin into communicative contact with a the bus line so that at least one input/output line from the first hardware model is connected to an input/output line of the second hardware model.
61 citations
TL;DR: In this article, a bus-following model with consideration of an on-line bus station based on the properties of each bus's motion is developed. But the model is not suitable for the case of large numbers of passengers.
Abstract: In this paper, we developed a bus-following model with consideration of an on-line bus station based on the properties of each bus’s motion. The numerical results show that the proposed model can qualitatively describe the effects of an on-line bus station on each bus’s motion.
61 citations
TL;DR: A performance analysis and experimental simulation results on the problem of scheduling a divisible load on a bus network and a software support system with flexibility in terms of scalability of the network and the load size are presented.
61 citations