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Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.


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Patent
Ernst August Munter1
09 Nov 1981
TL;DR: In this article, a non-blocking switching network for use in a TDM (time division multiplex) system for switching digital signals carried on incoming buses to outgoing buses (e.g. in a telephone switching office) is disclosed.
Abstract: A non-blocking switching network for use in a TDM (time division multiplex) system for switching digital signals carried on incoming buses to outgoing buses (e.g. in a telephone switching office) is disclosed. In one embodiment the digital signals, on each pair of incoming buses, are alternately stored in two memory devices. During "even" frames the digital signals from a first incoming bus of the pair are stored in a first memory device and during "odd" frames the digital signals from the first incoming bus of the pair are stored in a second memory device. Similarly, during the "even" frames the digital signals from the second incoming bus of the pair are stored in the second memory device and during the "odd" frames the digital signals from the second incoming bus of the pair are stored in the first memory device. Also, during "even" frames the first outgoing bus is responsive to signals stored in the first memory device and during "odd" frames is responsive to the signals stored in the second memory device. Similarly, during "even" frames the second outgoing bus is responsive to signals stored in the second memory device and during "odd" frames is responsive to the signals stored in the first memory device.

58 citations

Patent
14 Oct 2009
TL;DR: In this paper, the authors present a method for detecting a transition of a control bus from a high state to a low state by a source device, the source device being configured to be coupled with a sink device via an interface.
Abstract: Discovery of connections utilizing a control bus. An embodiment of a method includes detecting a transition of a control bus from a high state to a low state by a source device, the source device being configured to be coupled with a sink device via an interface, the interface including the control bus, the source device including a pullup device and the sink device including a pulldown device;pulsing the control bus to a high state at the source device; and upon detecting by the source device that the control bus remains in the high state ceasing the pulsing of the control bus to the high state, and transitioning the source device from a disconnected state to a connected state.

58 citations

Patent
09 Jun 1997
TL;DR: In this paper, the authors propose a network system that provides a scaleable and distributed architecture to enable a plurality of remote clients to access a local area network (LAN), which includes an access server that executes a network operating system (NOS), an access bus, an access device coupled to the access server and the access bus that cooperates with the NOS to establish a communication link between the access servers and the clients.
Abstract: A network system that provides a scaleable and distributed architecture to enable a plurality of remote clients to access a local area network (LAN). The network system includes an access server that executes a network operating system (NOS), such as any standard NOS, to enable communication with the LAN, an access bus, an access device coupled to the access server and the access bus that cooperates with the NOS to establish a communication link between the access server and the clients, and at least one multiport device coupled to the access bus and coupled to one or more clients through corresponding wide area network (WAN) connections that cooperates with the access device to establish a communication link between clients and the access device. The access server is preferably implemented on an industry standard platform using industry standard components. The access bus is either a dedicated bus or a shared media bus, such as Ethernet. The multiport and access devices cooperate to link each client to the access server as though directly connected thereto. Each multiport device includes a plurality of port slots, each for receiving one of a plurality of communication cards coupled to a remote clients via corresponding WAN connections. Each communication card operates according to one of a plurality of different communication protocols.

58 citations

Patent
05 Feb 1998
TL;DR: In this paper, a high-speed processor system with a bus arbitration mechanism constructed on a single semiconductor chip is presented, where the bus arbitrator receives a bus request signal from each bus master that requests the bus access and issues a bus grant signal to the bus master allowed to access the bus.
Abstract: A high-speed processor system having a bus arbitration mechanism constructed on a single semiconductor chip. The processor system comprises at least one bus master, a plurality of buses and a plurality of bus slaves. Each bus comprises an independent address bus, an independent data bus and individual data transfer capability. Every bus master comprises a plurality of independent bus interfaces each connected to one of the buses. Each bus slave is connected to a bus that has corresponding data transfer capability. For a system having more than two bus masters, the system further comprises a plurality of bus arbitrators for arbitrating the access of each bus independently. The bus arbitrator receives a bus request signal from each bus master that requests the bus access and issues a bus grant signal to the bus master allowed to access the bus. The bus arbitrator comprises a plurality of priority order information storage devices for storing priority order information for all the bus masters connected to the bus. At every bus cycle, one set of priority order information is selected continuously and cyclically. When more than one bus master requests the bus access at the same time, the bus arbitrator determines which bus master may access the bus according to selected priority order information.

58 citations

Journal ArticleDOI
TL;DR: In this article, a sensitivity analysis approach is used for selecting the buses for the placement of distributed generations operating at unity power factor, which is done in two ways i.e., non-sequential placement and sequential placement of DG in a distribution network.
Abstract: This paper presents the reconfiguration of the distribution network in the presence of distributed generations (DGs) by considering two bus types i.e., P bus and PQV bus (remotely voltage controlled bus). The ‘P’ bus is represented by active power specification only whereas the PQV bus is one whose voltage is remotely controlled by the P bus. A methodology is proposed to select the P bus for controlling the voltage magnitude of remotely located PQV bus. A sensitivity analysis approach is used for selecting the buses for the placement of DGs operating at unity power factor. The placement of DGs is done in two ways i.e., non-sequential placement and sequential placement of DG in a distribution network. Genetic algorithm (GA) technique is used for the optimization of DGs followed by network reconfiguration. The objective function for network reconfiguration in this paper is considered to be real power loss reduction. Effectiveness of the proposed method is demonstrated through examples of 33 bus and 69 bus distribution networks.

58 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202229
202192
202093
201999
2018108