Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.

Reconfigureable network node

Abstract: Nodes in a network having a plurality of nodes establish communication links with other nodes using available transmission media, as the ability to establish such links becomes available and desirable. The nodes predict when existing communications links will fail, become overloaded or otherwise degrade network effectiveness and act to establish substitute or additional links before the node's ability to communicate with the other nodes on the network is adversely affected. A node stores network topology information and programmed link establishment rules and criteria. The node evaluates characteristics that predict existing links with other nodes becoming unavailable or degraded. The node then determines whether it can form a communication link with a substitute node, in order to maintain connectivity with the network. When changing its communication links, a node broadcasts that information to the network. Other nodes update their stored topology information and consider the updated topology when establishing new communications links for themselves.

Multiple path multiplexed host to network data communication system

Abstract: A data transfer controller allows data to be transferred from a network bus to a system bus in a host computer. The controller has a network bus interface for communicating with the network bus and a system bus interface for communicating with the system bus. The system bus interface has first and second buffers. A dual port memory is utilized and has one port operatively connected to one of the buffers in the system bus interface and to a microprocessor. The direct access channel is established and operatively connected to the other buffer of the system bus interface as well as coupled to the microprocessor and associated control logic. A switch under control of the control logic establishes connections between the second port of the dual port memory and either the direct access channel or the network bus interface.

A cost-minimization model for bus fleet allocation featuring the tactical generation of short-turning and interlining options

Abstract: Urban public transport operations in peak periods are characterized by highly uneven demand distributions and scarcity of resources. In this work, we propose a rule-based method for systematically generating and integrating alternative lining options, such as short-turning and interlining lines, into the frequency and resource allocation problem by considering the dual objective of (a) reducing passenger waiting times at stops and (b) reducing operational costs. The bus allocation problem for existing and short-turning/interlining lines is modeled as a combinatorial, constrained and multi-objective optimization problem that has an exponential computational complexity and a large set of decision variables due to the additional set of short-turning/interlining options. This constrained optimization problem is approximated with an unconstrained one with the use of exterior point penalties and is solved with a Genetic Algorithm (GA) meta-heuristic. The modeling approach is applied to the bus network of The Hague with the use of General Transit Feed Specification (GTFS) data and Automated Fare Collection (AFC) data from 24 weekdays. Sensitivity analysis results demonstrate a significant reduction potential in passenger waiting time and operational costs with the addition of only a few short-turning and interlining options.

Communication apparatus and method between distributed objects

Abstract: Disclosed is a communication apparatus between distributed objects comprising: a plurality of separate software buses adapted to determine whether or not a communication service of which function and property is provided in a distributed platform; a platform administrator adapted to build and administrate a communication architecture in the distributed platform; a bus manager adapted to manage both a standard of types of the plurality of software buses and a bus object instance in the distributed platform by a strategic plan and an instruction of the platform administrator; a bus trader adapted to provide a trade function through an interaction with the bus manager, and a client object and a server object of an application level; an object trader adapted to allow the client to dynamically find an appropriate server; a repository adapted to provide a function which stores persistently instance information and various types of the plurality of software buses; a bus adapter adapted to provide the client and server objects with an application programing interface (API) associated with a bus binding process for use of the distributed platform, and adapted to perform a necessary trade and the bus binding process through an interaction with the bus trader and the plurality of buses; and a bus factory adapted to create a bus object coinciding with the standard of types of the plurality of software buses.

Multiple interface input/output port allows communication between the interface bus of the peripheral device and any one of the plurality of different types of interface buses

Abstract: A multiple interface input/output port allows communication between an interface bus of a peripheral device and any one of a plurality of different types of interface buses that may be provided in a host computer. An interface bus detection circuit detects which type of interface bus the peripheral device is connected to on the host computer, and communications are then routed through an appropriate interface adapter that enables communication between the interface buses of the peripheral device and host computer. The interface bus detection circuit compares signal levels on selected ones of the lines of the interface bus of the host computer to a reference potential to determine which of the selected lines are grounded. The circuit then identifies the type of interface bus to which it is connected based on the determination of which of the selected lines of the interface bus are grounded.