Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.

Bus mastering interface control system for transferring multistream data over a host bus

Abstract: A bus interface control system and method includes an on-demand bus master interface for independently requesting multistream data from host memory without interrupting processing of the host processor between independent requests for data packets. A plurality of digital signal processors share the host bus and utilize flexible data speed transfer depending upon demand of real time data that must be transferred from host memory. The master interface control system includes an packet by packet arbitor to facilitate maximum throughput of data on-demand by the plurality of processing unit.

Data processing system including buffering mechanism for inbound and outbound reads and posted writes

Abstract: A data processing system includes a host processor, a number of peripheral devices, and one or more bridges which may connect between the host, peripheral devices and other hosts or peripheral devices such as in a network. Each bus to bus bridge connects between a primary bus and a secondary bus wherein for the purpose of clarity, the primary bus will be considered as the source for outbound transactions and the destination for inbound transactions and the secondary bus would be considered the destination for outbound transactions and the source for inbound transactions. Each bus to bus bridge includes an outbound data path, an inbound data path, and a control mechanism. The outbound data path includes a queued buffer for storing transactions in order of receipt from the primary bus where the requests in the queued buffer may be mixed as between read requests and write transactions , the outbound path also includes a number of parallel buffers for storing read reply data and address information. The inbound path is a mirror image of the outbound path with read requests and write requests being stored in a sequential buffer and read replies being stored in a number of parallel buffers. Both the inbound path and the outbound path in the bus to bus bridge are controlled by a state machine which takes into consideration activity in both directions and permits or inhibits bypass transactions.

Method and apparatus for communicating data across a bus bridge upon request

Abstract: A method of a processor communicating data across a bus bridge to a processing apparatus on a bus including the steps of storing the data into a processor memory, notifying the bus bridge, coupled to the processor and a bus, that the data is in the processor memory, reading the data from the processor memory upon request of the bus bridge, and forwarding the data from the bus bridge to the processing apparatus across the bus. In addition, an apparatus for a processor to communicate data across a bus bridge to a processing means on a bus including an apparatus for storing the data into a processor memory, an apparatus for notifying the bus bridge, coupled to the processor and a bus, that the data is in the processor memory, an apparatus for reading the data from the processor memory upon request of the bus bridge, and an apparatus for forwarding the data from the bus bridge to the processing apparatus across the bus.

Method and apparatus for bridging a plurality of buses and handling of an exception event to provide bus isolation

Abstract: A bus bridge coupled between two bridges providing bus exception event isolation and address/data translation. In one embodiment the bus bridge includes two direct memory access (DMA) engines and a first-in-first-out (FIFO) buffer interface between the DMA engines to provide the bus exception isolation. The DMA engines and FIFOs also enable a packet based message passing architecture, which eliminates the need for address translation and also handles data reordering.

Method of data arbitration and collision detection in a data bus

Abstract: A method of blocking data transmission from a user microprocessor to a data bus utilizing arbitration and collision detection in a data bus interface integrated circuit utilizing a Serial Communication Interface (SCI) port on the user microprocessor.