Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.

Method and apparatus for dynamically allocating bandwidth on a TDM bus

Abstract: The present invention relates to methods and apparatus providing for a switching hub in which an asynchronous transfer mode (ATM) switch is utilized as a backplane bus. Bus arbitration, i.e., allocation of bandwidth, on the bus for autonomous ATM and LAN switching modules coupled thereto is dynamically controlled according to the needs of the various modules. In particular, the present invention allows time division multiplexing of the bus under programmatic control such that each module, e.g., an Ethernet or Token Ring module, is allowed a desired number of cell slots on the bus during which to transfer data, which the module has translated into ATM cells, across the bus.

Using intelligent agents for Transportation Regulation Support System design

Abstract: This paper presents an agent-based approach used to design a Transportation Regulation Support System (TRSS), that reports the network activity in real-time and thus assists the bus network regulators. The objective is to combine the functionalities of the existing information system with the functionalities of a decision support system in order to propose a generic model of a traffic regulation support system. Unlike the other approaches that only deal with a specific task, the original feature of our generic model is that it proposes a global approach to the regulation function under normal conditions (network monitoring, dynamic timetable management) and under disrupted conditions (disturbance assessment and action planning of feasible solutions). Following the introduction, the second section presents the notions of the domain and highlights the main regulation problems. The third section details and motivates our choice of the components of the generic model. Based on our generic model, in the fourth section, we present a TRSS prototype called SATIR (Systeme Automatique de Traitement des Incidents en Reseau - Automatic System for Network Incident Processing) that we have developed. SATIR has been tested on the Brussels transportation network (STIB). The results are presented in the fifth section. Lastly, we show how using the multi-agent paradigm opens perspectives regarding the development of new functionalities to improve the management of a bus network.

Methods and apparatus for enabling bus connectivity over a data network

Abstract: A method and system for interconnecting peripherals, processor nodes, and hardware devices to a data network to produce a network bus providing OS functionality for managing hardware devices connected to the network bus involves defining a network bus driver at each of the processor nodes that couples hardware device drivers to a network hardware abstraction layer of the processor node. The network bus can be constructed to account for the hot-swappable nature of the hardware devices using a device monitoring function, and plug and play functionality for adding and, removing device driver instances. The network bus can be used to provide a distributed processing system by defining a shared memory space at each processor node. Distributed memory pages are provided with bus-network-wide unique memory addresses, and a distributed memory manager is added to ensure consistency of the distributed memory pages, and to provide a library of functions for user mode applications.

Register bus multiprocessor system with shift

Abstract: A digital data processing apparatus includes a shift-register bus that transfers packets of digital information. The bus has a plurality of digital storage and transfer stages connected in series in a ring configuration. A plurality of processing cells, each including at least a memory element, are connected in a ring configuration through the bus, with each cell being in communication with an associated subset of stages of the bus. At least one processing cell includes a cell interconnect that performs at least one of modifying, extracting, replicating and transferring a packet based on an association, if any, between a datum identified in that packet and one or more data stored in said associated memory element. The cell interconnect responds to applied digital clock cycle signals for simultaneously transferring at least a selected packet through successive stages of the bus at a rate responsive to the digital clock cycle rate, while performing the modifying, extracting, replicating and transferring operation.

Decentralized bus arbitration using distributed arbiters having circuitry for latching lockout signals gated from higher priority arbiters

Abstract: A silicon semiconductor wafer containing a plurality of silicon integrated circuits formed therein or attached thereto contains at least one data bus to which some of the circuits are connected. Each of the circuits coupled to the data bus contains an arbitration request circuit which selectively passes a signal that requests that its circuit be given access to the data bus so it can transmit information to another circuit on the wafer. In addition, each of the circuits coupled to the data bus has an arbitration circuit which detects which of any of the circuits coupled to the data bus is requesting access to the data bus and facilitates its circuit gaining access to the data bus if its circuit has a higher preselected priority than any other circuit which is simultaneously seeking access to the data bus. The distribution of the arbitration request circuits and of the arbitration circuits simplifies layout and tends to improve the speed of operation.