Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.

Hybrid Artificial Bee Colony Algorithm for Transit Network Design

Abstract: A hybrid enhanced artificial bee colony algorithm (HEABC) is proposed for solving the problem of bus network design. The algorithm is intended to reduce the weighted sum of the number of transfers and the total travel time of the users through restructured bus routes and new frequencies without increased fleet sizes. The HEABC relies mainly on the enhanced artificial bee colony algorithm to determine the route structure, and the frequency is determined by the frequency-setting heuristic during the fitness evaluation. For an illustration of its performance, the HEABC was compared with a hybrid generic algorithm and a variant of the HEABC. The results indicated that the HEABC could produce better solutions than the other two algorithms could. Moreover, the HEABC could produce a design that was better than the existing design for maximum intermediate stops, total travel time, number of transfers, maximum headway, and total fuel cost. The design should be acceptable to the public and to bus operators.

High-speed dominant mode bus for differential signals

Abstract: A bus circuit for implementing a high speed dominant logic bus for a differential signal. The bus circuit is useful in a communication network having a plurality of multi-port nodes that are coupled by point-to-point links that communicate differential signals. Each port (30) in the node includes a bus driver (150) that receives the differential signal received at the port. The bus driver supplies a differential current signal to a first bus (40). A terminator circuit (50) is coupled to the first differential bus, to receive the differential current signals supplied from the ports. The terminator circuit, responsive to the differential current signal, outputs a differential voltage signal indicative of either a dominant state or a non-dominant state to a second differential bus (42), which is coupled to the plurality of ports for transmission. A biasing circuit (80) for the bus drivers allows operation at low voltages, and furthermore insures that the zero crossing of the differential input signals is equivalent to the zero crossing of the differential voltage signal on the second differential bus.

Method and arrangement for detecting faults in a network

Abstract: The present invention relates to an arrangement and a method for detecting faults in an optical fiber network, comprising at least two nodes arranged with at least two optical fibers to a bus with the end nodes connected via two spare fibers. Every node comprising a central module (50), at least two protection switches (60,61) and optical amplifiers (21,22,23,24) and said central module comprising at least one central processor (51), at least one logical unit (52), at least one protection signal transmitter (53) and at least one protection signal monitor (54). The end nodes of the bus transmit a protection signal in at least one direction of the bus and said end nodes can detect the own protection signal and the protection signal transmitted from the other end node. All nodes in the bus can detect Optical Power Loss, OPL. The bus will reshape into new end nodes in case of a fault.

Scalable on-chip system bus

Abstract: An on-chip split transaction system bus having separate address and data portions is provided. The system bus contains separate address and data buses for initiating and tracking out-of-order transactions on either or both of the address or data portions of the bus. The system bus provides communication via a bus interface that includes split transaction tracking and control to establish transaction ID's for each transaction initiated by the bus interface, and to determine whether data appearing on the data portion of the system bus is associated with one of its pending transactions. The bus interface also contains flow control logic to determine whether devices that are to be read from, or written to, by the bus interface, have resources (buffers) available to respond to the transactions. If the resources are available, the flow control logic allows the transactions to proceed, and adjusts its counters to reflect the use of the resources. If the resources are not available, the flow control logic causes the transactions to wait until the resources become available.

Real-time communications in a computer-controlled workcell

Abstract: A computer-integrated manufacturing (CIM) system is composed of several workcells, each of which contains robots, numerical-control machines, sensors, and a transport mechanism. The author considers a communication subsystem that is designed to support real-time control and coordination of devices in each CIM cell. The concept of a poll number is proposed to control the access to the intracell bus. The bus access mechanism with the poll number is intended to minimize the probability of real-time messages missing their deadlines. Use of a poll number provides not only for decentralized control of the intracell bus, but also a high degree of flexibility in scheduling messages. The performance of the bus access mechanism with a poll number is analyzed and compared with that of a token bus which is widely used in CIM systems such as MAP (Manufacturing Automation Protocol) networks. The probability of a real-time message missing its deadline in a token bus is found to be much higher than that of the proposed mechanism. >