Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.

Computer system with bridge logic that includes an internal modular expansion bus and a common target interface for internal target devices

Abstract: A computer system includes a CPU and a memory device coupled by a North bridge logic unit to an expansion bus, such as a PCI bus. A South bridge logic connects to the expansion bus and couples various secondary busses and peripheral devices to the expansion bus. The South bridge logic includes internal control devices that are targets for masters on the expansion bus. The target devices couple to the expansion bus through a common expansion target interface, which monitors and translates master cycles on the expansion bus on behalf of the target devices. The South bridge also includes an internal modular target expansion bus coupling the internal target devices to the common target interface. The internal modular target expansion bus permits the target devices to receive master cycles from any expansion bus by understanding a standardized group of signals represented by the internal modular target expansion (IMAX) bus. The target interface then is responsible for understanding the protocol of the expansion bus and converting the expansion bus signals to IMAX target bus signals. The IMAX target bus includes both an inbound bus and an outbound data bus for driving out data requested as part of a read cycle to an internal target device.

ATM switch with integrated system bus

Abstract: A network switch includes a plurality of cell processing units coupled together via a switch bus. In a preferred embodiment, the switch bus supports the peripheral component interconnect (PCI) bus protocol. Each cell processing unit includes a segmentation and reassembly unit (SAR), a RISC processor, a port processor, and a bus control unit. The SAR generates cells from frames of data stored in memory and transfers those cells to a destination mailbox in response to commands from from the RISC processor. The SAR assembles a cell within an internal register by combining cell header information with payload data read from memory. Once a cell has been assembled, it is sent to the bus controller for transmission across the switch bus to an address given by a mailbox number. Cells are transferred across the switch bus using a PCI burst write to the mailbox. A reassembly function gathers 48-byte cells into one or more larger output buffers. Cell reassembly is triggered by another RISC processor command. During reassembly, cell header information is discarded and the data payload bytes are read to an internal buffer within the SAR. The payload data is then written to a memory location pointed to by a buffer memory pointer. The switch bus 14 is also used for the transfer of control information between configuration registers of the cell processing units 12.

System for dynamically reconfiguring subbusses of data bus according to system needs based on monitoring each of the information channels that make up data bus

Abstract: A data bus for connecting information processing devices is configurable into a plurality of subbusses in order to fully utilize the data bus capacity. The size and data transfer direction of each subbus, as well as the data transfer speed of each subbus, is independent of the other subbusses. Also, the data bus can be reconfigured to meet changing system requirements. A data bus controller is thus provided to accomplish this data bus reconfiguration. The reconfiguration may be accomplished in accordance with one of a plurality of information flow templates which may be stored in a memory. A method of configuring a data bus is also provided wherein information transfer needs of a system are identified and the data bus is configured according to the identified information transfer means. The reconfiguration in accordance with the information transfer needs may be accomplished in accordance with one or more information flow templates which may be stored in a memory. The system may operate in accordance with a self arbitration scheme such that reconfiguration of the system is based on operational experience, such as utilization rates or excess capacity associated with each of the subbusses.

Method and apparatus for bus bandwidth management

Abstract: A computer system includes bus bandwidth management for operation of a high-speed bus. The high-speed bus is coupled to a plurality of modules. A plurality of client applications operate on the computer system, and request services from the high-speed bus to transfer data from a source module to at least one destination module. The bus bandwidth management system contains a bus manager, a dispatcher, a global controller, and a local controller contained on each module. Transfer requests for data transfer on the high-speed bus are made from the client applications to the bus manager. The bus manager takes the requested information and, based on a bus management policy management in effect, schedules a transfer order for the transfer requests. The bus manager then transfers the ordered transfer requests to the dispatcher. The dispatcher decomposes the ordered transfer requests into individual bus transfer operations. For each individual bus transfer operation, the dispatcher loads a command packet into the global controller, the source module, and the destination module(s). After the dispatcher dispatches all individual bus transfer operations, the dispatcher returns to the bus manager to receive the next transfer request. The global controller executes the individual bus transfer operations in the transfer order.

Backplane data transfer technique for industrial automation controllers

Abstract: A bus structure for interconnecting the modules of an industrial automation controller includes DATA lines and associated control lines that enable interface circuits on each module to transfer frames of data. Modules connected to the bus structure support data transfers of differing widths and differing speeds, and interface circuits within each module automatically adapt to data width and speed differences between communicating modules. During a first bus cycle of each transfer, sending and receiving modules negotiate a bus width and clock speed to be used for the transfer by asserting their respective width and speed codes onto a set of wired-or status lines. After the first bus cycle, the status lines are then used for communicating alternate functions between the participating modules.