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Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.


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Patent
24 Jan 1992
TL;DR: In this paper, a method and apparatus for controlling a dual bus system, capable of realizing high speed and continuous operation even if one of the buses of the dual bus systems fails.
Abstract: A method and apparatus for controlling a dual bus system, capable of realizing high speed and continuous operation even if one of the buses of the dual bus system fails. The method and apparatus has a dual bus system, a plurality of electronic circuits connected to both buses of the dual bus system, and bus controller for providing a bus use allowance signal to one of the plurality of electronic circuits, the one electronic circuit being selected in accordance with bus occupation request signals issued from the plurality of electronic circuits requesting data transfer. If the bus occupation request signals for both buses of the dual bus system originates from the one selected electronic circuit and the outputs of the arbiters coincide, the bus use allowance signal is provided to the one selected electronic circuit for the allowance of occupying both buses of the dual bus system. A completion of data transfer at the dual bus system is determined when data transfer is completed at both buses. Continuous operation can be ensured immediately upon occurrence of a failure, and high speed operation of a computer system is possible.

51 citations

Patent
29 Oct 1993
TL;DR: In this paper, an access operation is executed in a pipeline mode via buses to which bus masters are connected, and a control of the pipeline execution is performed by a bus controller.
Abstract: In a microcomputer system, an access operation is executed in a pipeline mode via buses to which bus masters are connected, and a control of the pipeline execution is performed by a bus controller. Furthermore, an access for delaying this pipeline operation is carried out by low-level of hierarchical buses connected by a buffer and a low-level bus controller.

51 citations

Patent
26 Jan 1988
TL;DR: In this paper, a high speed serial bus is described and a message controller is coupled to each agent for transmitting and receiving serial data along the bus, which provides three basic signal outputs: the bus state detector determines whether or not the bus is in use, a collision has occurred between messages, and decoding data received on the bus.
Abstract: A high speed serial bus is disclosed have particular application for use in passing messages in a multiple processor computer system. The serial bus includes a three-wire serial link having lines identified as "SDA", "SDB" and "ground". The ground line provides a common reference for all devices coupled to the serial bus. A message controller is coupled to each agent for transmitting and receiving serial data along the bus. Both lines of the serial bus as well as the ground are coupled to a bus state detector in the message controller which provides three basic signal outputs. The bus state detector determines whether or not the bus is in use, a collision has occurred between messages, and decodes data received on the bus. Data which is transmitted along the serial bus is driven on lines SDA and SDB 180 degrees out of phase relative to each other. The message controller encodes messages to be transmitted using, in the present embodiment, well known Manchester encoding techniques. A bus idle state occurs when all transmitters are off allowing both lines SDA and SDB be pulled high by pull-up resistors. Valid data states may occur any time a single transmitter is transmitting. When two or more transmitters begin transmitting a collision state exists. The message controller recognizes collisions and provides a back-off algorithm.

51 citations

Patent
29 Jun 2001
TL;DR: In this article, a method and associated apparatus is provided for improving the performance of a high speed memory bus using switches, where switches disconnect unused bus segments during operations so that communicating devices are connected in an substantially point-to-point communication path.
Abstract: A method and associated apparatus is provided for improving the performance of a high speed memory bus using switches. Bus reflections caused by electrical stubs are substantially eliminated by connecting system components in a substantially stubless configuration using a segmented bus wherein bus segments are connected through switches. The switches disconnect unused bus segments during operations so that communicating devices are connected in an substantially point-to-point communication path.

51 citations

Journal ArticleDOI
TL;DR: In this paper, the problem of designing efficient bus synchronization into a timetable is addressed, where the scheduler attempts to create the departure times in the timetable while complying with the required frequency, efficient assignment of trips to a single bus chain and synchronization of certain arrivals.
Abstract: The problem of designing efficient bus synchronization into a timetable is addressed. Synchronization means a fit between the arrival time of one bus to the departure time of another bus, so that passengers can transfer from one bus to another. Synchronization is the most difficult task of transit schedulers and is addressed intuitively. The scheduler, in fact, attempts to create the departure times in the timetable while complying with the required frequency, efficient assignment of trips to a single bus chain, and synchronization of certain arrivals. Efficient procedures are presented for applying maximum synchronization as a useful tool for the scheduler in creating timetables. These procedures attempt to maximize the number of simultaneous bus arrivals at the connection (transfer) points of the bus network. Accounting for user satisfaction and convenience, transit schedulers appreciate the importance of creating a timetable with maximum synchronization, which enables the transfer of passengers from one route to another with minimum wait time at transfer nodes. Efficient procedures are described to create the maximum, simultaneous bus arrivals, and a series of examples is presented to illustrate the procedures.

51 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202229
202192
202093
201999
2018108