Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.

Distributed arbitration on a full duplex bus

Abstract: Distributed arbitration in a full duplex bus system (32, 34). By distributing the arbitration function among the nodes of a tree topology full duplex bus system such that arbitration (16) at any particular time is handled by a node holding a grant of the bus at that time (the nominal root node), a reverse flow direction towards the nominal root node (10) is available for arbitration flow. This allows the discrete arbitration phase to be eliminated and generally improves bus efficiency.

Single wire bus for connecting devices and methods of operating the same

Abstract: A master/slave system architecture including a single wire bus and master device and bus interface coupled to the bus. The system further includes slave devices having respective bus interfaces coupled to the bus. The system further includes a communication protocol implemented over the single wire bus and employed by the master and the slave devices. The protocol includes bus transactions for communicating between the master and the slave devices. The communication protocol further includes Master Slave Operational Interface (MSOI) that includes repertoire of functions properties stored in the master device, whereby, the master can communicate with any slave device that supports functions properties that belong to the repertoire of functions properties, using the bus transactions, substantially without need of retrofit.

System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding

Abstract: A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an upstream data bus. The memory hub controller includes a receiver coupled to the upstream data bus and a transmitter coupled to the downstream data bus. Similarly, each of the memory modules includes a receiver coupled to the downstream data bus and a transmitter coupled to the upstream data bus. Each receiver includes a receive clock generator that is synchronized by coupling a known pattern of data to the receiver. The receiver determines which phase of the receive clock best captures the known pattern and uses that receive clock phase during normal operation.

A Novel Line Stability Index for Voltage Stability Analysis and Contingency Ranking in Power System Using Fuzzy Based Load Flow

Abstract: In electric power system, the line stability indices adopted in most of the instances laid stress on variation of reactive power than real power variation of the transmission line. In this paper, a proposal is made with the formulation of a New Voltage Stability Index (NVSI) which originates from the equation of a two bus network, neglecting the resistance of transmission line, resulting in appreciable variations in both real and reactive loading. The efficacy of the index and fuzzy based load flow are validated with IEEE 30 bus and Tamil Nadu Electricity Board (TNEB) 69 bus system, a practical system in India. The results could prove that the identification of weak bus and critical line in both systems is effectively done. The weak area of the practical system and the contingency ranking with overloading either line or generator outages are found by conducting contingency analysis using NVSI.

Three level direct communication connections between neighboring multiple context processing elements

Abstract: A method and an apparatus for configuration of multiple context processing elements (MCPEs)are described. According to one aspect of the invention, the structure that joins the MCPE cores into a complete array in one embodiment is actually a set of several mesh-like interconnect structures. Each interconnect structure forms a network, and each network is independent in that it uses different paths, but the networks join at MCPE input switches. The network structure of one embodiment of the present invention is comprised of a local area broadcast network (level 1), a switched interconnect network (level 2), a shared bus network (level 3), and a broadcast network. In one embodiment, the level 3 network is used to carry configuration data for the MCPEs while the broadcast network is used to carry configuration data for the level 3 network drivers and switches. In one embodiment, the level 3 network is bidirectional and dynamically routable.