Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.

Central processing apparatus for fault-tolerant computing

Abstract: A fault-tolerant computer system provides information transfers between the units of a computing module, including a processor unit and a memory unit and one or more peripheral control units, on a bus structure common to all the units. Information-handling parts of the system, both in the bus structure and in each unit, can have a duplicate partner. Error detectors check the operation of the bus structure and of each system unit to provide information transfers only on fault-free bus conductors and between fault-free units. The computer system can operate in this manner essentially without interruption in the event of faults by using only fault-free conductors and functional units. Arbitration circuits of unusual speed and simplicity provide units of the computing module with access to the common bus structure according to the priority of each unit. The units of a module check incoming and outgoing signals for errors, signal other module units of a detected error, and disable the unit from sending potentially erroneous information onto the bus structure.

Demand Assignment Multiple Access Schemes in Broadcast Bus Local Area Networks

Abstract: Local area communications networks based on packet broadcasting techniques provide simple architectures and efficient and flexible operation. Various ring systems and CSMA contention bus systems have been in operation for several years. More recently, a number of distributed demand assignment multiple access (DAMA) schemes suitable for broadcast bus networks have emerged which provide conflict-free broadcast communications by means of various scheduling techniques. Among these schemes, the Token-Passing Bus Access method uses explicit tokens, i.e., control messages, to provide the required scheduling. Others use implicit tokens, whereby stations in the network rely on information deduced from the activity on the bus to schedule their transmissions. In this paper we present many implicit-token DAMA schemes in a unified manner grouped according to their basic access mechanisms, and compare them in terms of performance and other important attributes.

An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration

Abstract: In this paper we present a network interface for an on-chip network. Our network interface decouples computation from communication by offering a shared-memory abstraction, which is independent of the network implementation. We use a transaction-based protocol to achieve backward compatibility with existing bus protocols such as AXI, OCP and DTL. Our network interface has a modular architecture, which allows flexible instantiation. It provides both guaranteed and best-effort services via connections. These are configured via network interface ports using the network itself, instead of a separate control interconnect. An example instance of this network interface with 4 ports has an area of 0.143 mm/sup 2/ in a 0.13 /spl mu/m technology, and runs at 500 MHz.

Finding Maximum on an Array Processor with a Global Bus

Abstract: The problem of finding the maximum of a set of values stored one per processor on an n X n array of processors is analyzed. The array has a time-shared global bus in addition to conventional processor-processor links. A two-phase algorithm for finding the maximum is presented that uses conventional links during the first phase and the global bus during the second. This algorithm is faster than algorithms that use either only the global bus or only the conventional links.

Detection and identification of topology errors in electric power systems

Abstract: A method for detecting topology errors in electric power networks is developed by providing a geometric interpretation of the measurement residuals caused by such errors. A test for single topology errors is presented that is similar to the normalized residuals test for measurement errors. This test is generalized to multiple topology errors. The concept of critical network branches (where their removal renders the network unobservable) is introduced and extended to critical-branch k-tuples. It is shown that topology errors on critical branches cannot be detected from measurement residuals. An equation is developed for a matrix whose column linear dependencies determine topology error detectability and identifiability. An example for an IEEE 14 bus network is provided. >