Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.

Split computer architecture

Abstract: A network interface is described in which a single computer bus is split over a long distance into two or more inter-communicating buses. On one bus, processing and applications are provided and on the other remote bus, peripheral and local controllers are provided. The buses communicate through a series of: bridge, FPGA, FPGA and bridge. Between the FPGAs, a communication path provides long distance communication.

Method for and apparatus for operating a local communications module in arbitrating for mastership of a data transfer across a back plane bus in industrial automation controller

Abstract: A bus structure for interconnecting the modules of an industrial automation controller includes DATA lines and associated control lines that enable interface circuits on each module to send and receive frames of data. An arbitration circuit in each module employs arbitration lines in the bus structure to conduct a two phase competition to determine which module receives the next bus mastership. The arbitration lines include a set of wired-or weight code lines and a single arbitration strobe line. Modules desiring control of the bus structure assert a local weight code onto the weight code lines and determine which module is asserting the numerically greatest local weight code. Arbitration is conducted separately on the bus structure and a winning module is ready to transfer its data frame as soon as the previous winner completes its transfer and relinquishes control of the bus structure. The winning weight code identifies both the source address of the winning module and the priority of the data frame to be sent, and is latched by all modules on the backplane bus as an arbitration vector to provide advance identification of the next module to transmit and the priority of the message.

Redundant bus bridge systems and methods using selectively synchronized clock signals

Abstract: A redundant bus bridge system for communicating between a first bus and a second bus includes a first clock generator operative to produce a first clock signal and a second clock generator operative to produce a second clock signal. A first bus bridge, e.g., a first RAID controller, connects the first bus and the second bus and is responsive to the first clock generator and the second clock generator. The first bus bridge is operative to transfer data between the first bus and the second bus in synchronism with a selected one of the first clock signal and the second clock signal. A second bus bridge, e.g., a second RAID controller, connects the first bus and the second bus and is responsive to the first clock generator and the second clock generator. The second bus bridge is operative to transfer data between the first bus and the second bus in synchronism with a selected one of the first clock signal and the second clock signal. According to aspects of the present invention, the first bus bridge is operative to transfer data between the first bus and the second bus in synchronism with the second clock signal when the second bus bridge is operational, and the first bus bridge is operative to transfer data between the first bus and the second bus in synchronism with the first clock signal when the second bus bridge is non-operational.

System and method for avoiding bus contention on a multiplexed bus by providing a time period subsequent to a read operation

Abstract: A bus interface unit within a processor ensures a delay period after the occurrence of a read operation to avoid bus contention on a multiplexed bus, When there is a requirement for a back-to-back read or write operation subsequent to the read bus cycle on a multiplexed bus it is important to allow devices, such as memory, sufficient time to reset after transmission of data To avoid the bus contention problem that occurs after a read bus cycle, ie, prevent a next address on the bus until the bus is in a tri-state condition, one embodiment inserts idle clock cycles subsequent to a read but not subsequent to a write, The present invention avoids bus contention on a multiplexed bus while providing flexibility in interfacing with a variety of memory devices, and providing a flexible processor design

Optical communication network

Abstract: In an optical communication network in which a plural number of nodes are connected to each bidirectional broadcasting bus, and a node communicates with another using the packets, or an optical communication network in which a plural number of nodes are connected to a bidirectional broadcasting bus, and a node communicates with another using the packets, each node comprises carrier sensing means for sensing a carrier on the broadcasting bus, and jamming detecting means for detecting a jamming state of received signals.