Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.

Method for communicating data on a communication network by token passing

Abstract: A method of determining access on an electronic serial bus by implicit token passing. The serial bus receives and transmits data between a plurality of devices. Each device has a receiver for receiving data to the serial bus, a transmitter for transmitting data to the serial bus, a bus idle timer for detecting an idle condition on the bus, and a bus access timer for controlling access to the serial bus. Each device is assigned a unique bus address. The bus access timer of each device is loaded with a value representative of each device's own unique bus address and the unique bus address of the transmitting device. The bus access timer starts a count upon receiving an end of transmission condition from the transmitting device and stops upon receiving a start of transmission condition from the transmitting device. When a bus access timer of a device reaches a predetermined value, the device of the timed out bus access timer is given access to the bus.

Data bus transmission line termination circuit

Abstract: A data bus transmission line termination circuit for connection either to the terminal end of a data bus or to an intermediate portion of the bus. The circuit is programmable to either a low-impedance state for connection to the terminal end of the data bus so as to provide an optimum terminating load for the bus, or to a high-impedance state for connection to an intermediate portion of the data bus so as not to load down the latter when so connected. The termination circuit is preferably formed on the same integrated circuit chip as the receiver circuit so as to be located adjacent the effective end of the total transmission line including the portion extending from the data bus proper through the connections and conductors of the board, card, module and chip to the receiver circuit on the chip.

Multi-port network interface device with shared processing resources

Abstract: A network interface device includes a bus interface that communicates over a bus with a host processor and memory, and a network interface, including at least first and second physical ports, which are coupled to send and receive data packets carrying data over a packet network. A protocol processor includes a single transmit processing pipeline and a single receive processing pipeline, which are coupled between the bus interface and the network interface so as to convey the data between both of the first and second physical ports of the network interface and the memory via the bus interface while performing protocol offload processing on the data packets.

Data engine with metadata processor

Abstract: A programmable data path accelerator is described. The programmable data path accelerator operates on a file server that includes a network interface for communicating with one or more clients. The network interface includes a network transaction queue. A metafile processor is configured to communicate with the network interface across a first memory-mapped bus and is configured to communicate with the storage interface across a second memory-mapped bus. A data engine configured to communicate with the network interface across the first memory-mapped bus and to communicate with the storage interface across the second memory-mapped bus.

Data bus system for motor vehicles

Abstract: A data bus system for motor vehicles with a number of electronic bus stations, each having an input port that is connected to the motor vehicle battery to supply power to the bus stations. Each bus station is equipped with a detector circuit and a controllable switch. Each bus station is turned off in the ground state when the ignition is turned off, with the exception of the detector circuit assigned to it, by positioning the controllable switch into an open position in a selective wake state. The controllable switch of each selected bus station is closed by its detector circuit while the temporarily required data exchange between selected bus stations takes place. At least one of the bus stations is defined as the main bus station to control the wake state.