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Butterworth filter

About: Butterworth filter is a research topic. Over the lifetime, 6187 publications have been published within this topic receiving 69070 citations.


Papers
More filters
Journal ArticleDOI
TL;DR: This paper proposes current controlled differential difference current conveyor transconductance amplifier (CCDDCCTA), a new active building block for analog signal processing and demonstrates the usefulness of the proposed element through an application, namely, wave filter.
Abstract: This paper proposes current controlled differential difference current conveyor transconductance amplifier (CCDDCCTA), a new active building block for analog signal processing. The functionality of the proposed block is verified via SPICE simulations using 0.25 μm TSMC CMOS technology parameters. The usefulness of the proposed element is demonstrated through an application, namely, wave filter. The CCDDCCTA-based wave equivalents are developed which use grounded capacitors and do not employ any resistors. The flexibility of terminal characteristics is utilized to suggest an alternate wave equivalents realization scheme which results in compact realization of wave filter. The feasibility of CCDDCCTA-based wave active filter is confirmed through simulation of a third-order Butterworth filter. The filter cutoff frequency can be tuned electronically via bias current.

19 citations

Patent
Dong-Ook Chung1
TL;DR: In this article, a three-dimensional sound system and a method utilizing a head related transfer function (HRTF) for providing a threedimensional sound effect from a two-channel stereo signal source having first and second signals are disclosed.
Abstract: A three-dimensional sound system and a method utilizing a head related transfer function (HRTF) for providing a three-dimensional sound effect from a two-channel stereo signal source having first and second signals are disclosed The system includes a first high-pass filter for removing a direct current (DC) component from the first signal and a second high pass filter for removing a direct current (DC) component from the second signal The system includes a first FIR filter having a modified head related transfer function (HRTF) M1(e jw ) for re-localizing a first position of a sound source of the first signal input to the first high-pass filter to a second position The system also includes a second FIR filter having a modified HRTF M2(e jw ) for re-localizing a third position of a sound source of the second signal input to the second high-pass filter to a fourth position A first gain controller controls gain from an output signal from the first FIR filter, and a second gain controller controls gain from an output signal from the second FIR filter

19 citations

Proceedings ArticleDOI
03 Nov 1996
TL;DR: In this paper, a new design method for biorthogonal modulated filter banks is presented, based on a cascade of simple matrices, and it has some properties that have not been reported before.
Abstract: A new design method for biorthogonal modulated filter banks is presented. It is based on a cascade of simple matrices, and it has some properties that have not been reported before. It represents filter banks with arbitrary overall system delay and filter length, it is shown that almost all cosine modulated filter banks can be described by this structure, and that it leads to a more efficient implementation than previous structures. Imposing certain symmetries on the matrices can be used to design low delay filter banks with identical (except for the sign) baseband impulse responses for the analysis and synthesis filter bank.

19 citations

Journal ArticleDOI
TL;DR: A systematic analysis of baseband filter and analog-to-digital converter dynamic range in broadband receivers shows that low-order Butterworth filters are favorable when undesired power is dominated by far out blockers and high-order inverse Chebyshev filters can reduce the resolution of a subsequent ADC by up to two additional bits in the presence of adjacent analog narrowband blockers.
Abstract: An integrated ultrahigh-frequency (UHF) receiver is presented. A systematic analysis to quantify the interdependence of baseband filter and analog-to-digital converter (ADC) dynamic range in broadband receivers is presented. This analysis shows that: (1) low-order Butterworth filters are favorable when undesired power is dominated by far out blockers and (2) high-order inverse Chebyshev filters can reduce the resolution of a subsequent ADC by up to two additional bits in the presence of adjacent analog narrowband blockers. Based on the analysis, a cascaded, programmable, hybrid active-RC and switched-capacitor (SC) baseband filter is proposed. An all-digital nonoverlap clock tuning system to minimize the variation of available settling time window in SC circuits is also proposed. The receiver integrates the proposed filter with an RF variable gain amplifier (RFVGA) and a passive mixer. This receiver achieves a measured noise figure of 7.9 dB, an IIP3 of -8 dBm at maximum gain and +2 dBm at 9-dB RF attenuation. The chip consumes 120 mW (RFVGA, mixer and I-channel baseband) from 1.8-V analog/2.5-V digital dual supply and occupies 2.14 mm2 in IBM 0.18-μm RF CMOS technology.

19 citations

Patent
25 Jul 2000
TL;DR: In this paper, an infinite impulse response filter is used for compensating a velocity control loop having a filter section cascaded with an accumulator, and the filter is programmable in that filter coefficient(s) are dynamically received by the filter section.
Abstract: A disk drive having a motor and a velocity control loop, which includes a frequency detector and a filter. The filter includes a filter section and an accumulator. The filter is programmable in that filter coefficient(s) are dynamically received by the filter section. One embodiment of the filter section is an infinite impulse response filter. One embodiment of the filter is a digital integrated circuit. A method for compensating a control loop by infinite impulse response filtering and accumulating. The control loop may be a position, velocity, acceleration or force control loop. A programmable digital integrated circuit for compensating a velocity control loop having a filter section cascaded with an accumulator. The integrated circuit may include memory for storing filter coefficient(s) for the filter section, thereby not requiring external components.

19 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202322
202282
202140
202059
201941
201864