Showing papers on "Cache published in 1972"

Memory system with logical and real addressing

Abstract: A memory system is disclosed for use in a multiprocessing environment where each processor has associated with it a buffer memory and means are provided for one buffer to retain a modified copy of data. The contents of the buffer memory may be accessed by either real or logical addresses. Address translation means are provided to translate logical addresses. A fetch directory is provided to keep track of the data in cache. The fetch directory entries are accessed by both logical and real portions of the desired data address. Means are provided to insure that only one copy of data is maintained in the buffer although it may be entered at several cache locations dependent upon the logical address which last fetched the data.

Hierarchial memory system

Abstract: A large capacity, low speed backing store is organized to allow for high speed transfer of a block (page) of data to a cache associated with the Central Processing Unit (CPU). When a word is called out by the CPU, the other words in the same page are sequentially transferred to the intermediate buffer cache under the control of a ring circuit associated with the backing store. The first word transferred is the only word which must be specifically requested by the CPU; the transfer is accomplished at high speed within approximately the same machine time that the requested word is transferred from the backing store to the CPU.

Techniques for designing balanced, extensible computer systems

Abstract: : The study is concerned with a hierarchy of techniques for analyzing and determining minimum cost balanced, extensible time-shared multi-processor computer systems. A balanced system is defined as a system whose performance is insensitive to the variations in parameters specifying the user's and the program's behavior. An extensible system is defined as a system, whose capabilities are increased by the addition of components only such that the new system is a minimum cost, balanced, system. The hierarchy includes: PMS configuration, a multi-program model of a time-sharing computer system with paging or swapping strategies, the cache parameters and the actual cache structure at the gate level. A steady state model of a paging, time-shared, multi-processor c computer system is developed. Queuing theory is used to obtain the response time for user interaction, and given parameter attributes. (Modified author abstract)