Showing papers on "Cache algorithms published in 1973"

Cache-based Computer Systems

Abstract: A cache-based computer system employs a fast, small memory -the " cache" - interposed between the usual processor and main memory. At any given time the cache contains as much as possible the instructions and data the processor needs; as new information is needed it is brought from main memory to cache, displacing old information. The processor tends to operate with a memory of cache speed but with main memory cost-per-bit. This configuration has analogies with other systems employing memory hierarchies, such as "paging" or "virtual memory" systems. In contrast with these latter, a cache is managed by hardware algorithms, deals with smaller blocks of data (32 bytes, for example, rather than 4096), provides a smaller ratio of memory access times (5:1 rather than 1000: 1), and, because of the last factor, holds the processor idle while blocks of data are being transferred from main memory to cache rather than switching to another task. These are important differences, and may suffice to make the cache-based system cost effective in many situations where paging is not.

Cache store clearing operation for multiprocessor mode

Abstract: In a multiprocessor data processing system, all processors must have access to certain communications tables stored in the main memory shared by the processors. Each processor has a cache store embedded within for its individual use. A cache store in one processor might contain data from the communication tables which is obsoleted by operations of a second processor. The cache store clearing apparatus invalidates its data information any time its processor accesses the communication tables. The cache store is cleared by resetting tag directory indicators, a round robin counter and a column full flag, for each column in a four level set associative tag directory to the cache store. The data in the cache store need not be cleared. Using the four level set associative tag directory permits the data information in the cache store to be invalidated by a 16 pulse burst of signals for 1K words of cache store directed to the tag directory indicators.

Multi-processor system with multiple cache memories

Abstract: A digital data multi-processing system having a main memory operating at a first rate, a plurality of individual processors, each having its own associated cache memory operating at a second rate substantially faster than the first rate for increasing the throughput of the system. In order to control the access of the main memory by one of the plural processors to obtain information which may not be present in its associated cache memory, a Content Addressable Cache Management Table (CACMT) is provided.

Communications control apparatus for the use with a cache store

Abstract: A communications control apparatus prepares for the generation of an interrupt signal along with appropriate address signals to retrieve data information from the main memory store upon the request from the central processor. During preparation time, a tag directory is searched for an indication that the data information required is presently in the cache store. If a comparison is made, a match signal is generated to prevent the generation of the interrupt signal. The communications control apparatus addresses the cache store to retrieve the data information for use by the processor.