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Cache algorithms

About: Cache algorithms is a research topic. Over the lifetime, 14321 publications have been published within this topic receiving 320796 citations.


Papers
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Journal ArticleDOI
TL;DR: The authors propose a new instruction cache architecture for reducing dynamic energy consumption with negligible performance degradation, unlike typical architecture-level approaches which reduce dynamicEnergy consumption by sacrificing performance.
Abstract: An instruction cache consumes a significant amount of energy in modern microprocessors. Therefore energy efficiency as well as performance should be considered when designing instruction cache architecture, especially for embedded processors. The authors propose a new instruction cache architecture for reducing dynamic energy consumption with negligible performance degradation, unlike typical architecture-level approaches which reduce dynamic energy consumption by sacrificing performance. The proposed instruction cache is composed of two caches: a large main instruction cache and a small low-power trace cache (LPT-cache). When a request comes into the proposed cache, either main instruction cache or LPT-cache is only accessed by utilising the information from the modified branch target buffer which enables predictions with very high accuracy. The proposed technique reduces the dynamic energy consumption significantly by replacing the accesses to a large main instruction cache with those to a small LPT-cache. Simulation results show that the proposed technique reduces dynamic energy consumption by 14.6% on average with negligible performance degradation over the traditional instruction cache.

3 citations

Patent
25 Feb 2015
TL;DR: In this paper, the state of a cache portion identifier is captured to identify the cache portions that are within the application cache at an instant in time, and cache portions identified by the captured cache portion identifiers are automatically accessed from a source that is external to the application.
Abstract: The automated recovery of the warmth of cache of an application that has been subject to a running state change that degraded the warmth of the cache. To prepare for a loss in warmth, the state of a cache portion identifiers are captured. Such identifies the cache portions that are within the application cache at an instant in time. Thereafter, the application experiences a change in running state that diminishes the warmth of the application cache. For instance, the application might be stopped and restarted. After and despite this cache degradation, the application may continue to operate. However, in order to warm the application cache more quickly, while the application is operating, the application cache is automatically warmed. For instance, while the application is operating, cache portions identified by the captured cache portion identifiers are automatically accessed from a source that is external to the application cache.

3 citations

Patent
09 Nov 1999
TL;DR: In this article, a modified-unsolicited (MU) cache state is proposed to indicate that a value held in a cache line has been modified (i.e., is not currently consistent with system memory), but was modified by another processing unit, not by the processing unit associated with the cache that currently contains the value in the MU state, and that the value is held exclusive of any other horizontally adjacent caches.
Abstract: A novel cache coherency protocol provides a modified-unsolicited (M U ) cache state to indicate that a value held in a cache line has been modified (i.e., is not currently consistent with system memory), but was modified by another processing unit, not by the processing unit associated with the cache that currently contains the value in the M U state, and that the value is held exclusive of any other horizontally adjacent caches. Because the value is exclusively held, it may be modified in that cache without the necessity of issuing a bus transaction to other horizontal caches in the memory hierarchy. The M U state may be applied as a result of a snoop response to a read request. The read request can include a flag to indicate that the requesting cache is capable of utilizing the M U state. Alternatively, a flag may be provided with intervention data to indicate that the requesting cache should utilize the modified-unsolicited state.

3 citations

Proceedings ArticleDOI
04 Apr 2005
TL;DR: An inductive probability model is proposed to predict the impact of cache sharing on co-scheduled threads and is validated against a cycle-accurate simulation that implements a dual-core chip multi-processor (CMP architecture), on fourteen pairs of mostly SPEC benchmarks.
Abstract: The need to provide performance guarantee in high performance servers has long been neglected. Providing performance guarantee in current and future servers is difficult because fine-grain resources, such as on-chip caches, are shared by multiple processors or thread contexts. Although interthread cache sharing generally improves the overall throughput of the system, the impact of cache contention on the threads that share it is highly non-uniform: some threads may be slowed down significantly, while others are not. This may cause severe performance problems such as sub-optimal throughput, cache thrashing, and thread starvation for threads that fail to occupy sufficient cache space to make good progress. Clearly, this situation is not desirable when performance guarantee needs to be provided, such as in utility computing servers. Unfortunately, there is no existing model that allows extensive investigation of the impact of cache sharing. To allow such a study, we propose an inductive probability model to predict the impact of cache sharing on co-scheduled threads. The input to the model is the isolated L2 circular sequence profile of each thread, which can be easily obtained on-line or off-line. The output of the model is the number of extra L2 cache misses for each thread due to cache sharing. We validate the model against a cycle-accurate simulation that implements a dual-core chip multi-processor (CMP architecture), on fourteen pairs of mostly SPEC benchmarks. The model achieves an average error of only 3.9%.

3 citations

Proceedings ArticleDOI
03 Mar 2008
TL;DR: Four mode transition policies which aim at high energy reduction with the minimum performance degradation are proposed and compared with existing policies in the context of embedded processors.
Abstract: In the design of embedded systems, especially battery- powered systems, it is important to reduce energy consumption. Cache are now used not only in general-purpose processors but also in embedded processors. As feature sizes shrink, the leakage energy has contributed to a significant portion of total energy consumption. To reduce the leakage energy of cache, the Drowsy cache was proposed, in which the cache lines are periodically moved to the low- leakage mode without loss of its content. However, when a cache line in the low-leakage mode is accessed, one or more clock cycles are required to transition the cache line back to the normal mode before its content can be accessed. As a result, these penalty cycles may significantly degrade the cache performance, especially in embedded processors without out-of-order execution. In this paper, we propose four mode transition policies which aim at high energy reduction with the minimum performance degradation. We also compare our policies with existing policies in the context of embedded processors. Experimental results demonstrate the effectiveness of the proposed policies.

3 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202378
2022210
202146
202062
201970
2018103