Showing papers on "Cache coloring published in 1975"

Performance analysis of cache memories

Abstract: Using the Independent Reference assumption to model program behavior, the performance of different buffer organizations (Fully Associative, Direct Mapping, Set Associative. and Sector) are analyzed' (1) The expressions for their fault rate are derived To show more explicitly the dependence of the fault rate on the factors that affect it, distribution-free upper bounds on fault rates are computed for the Direct Mapping, Set Associative, and Sector buffers The use of such bounds is illustrated in the case of the Direct Mapping buffer (2) The performance of the buffers for FIFO and Random Replacement are shown to be identical (3) It is possible to restructure programs to take advantage of the basic organization of the buffers The effect of such restructuring is quantified for the Direct Mapping buffer It is shown that the performance of the Direct Mapping buffer under near-optimal restructuring is comparable to the performance of the Fully Associative buffer Further, the effect of this restructuring is shown to be potentially stronger than that of buffer replacement algorithms

The cost and performance tradeoffs of buffered memories

Abstract: An analysis of the performance enhancement achieved and the incremental costs accrued in buffering (using a cache memory) memory systems is made. Buffering is found to be cost-effective even for minicomputer memories. The study indicates that the flagged registered swap algorithm is superior to three other common algorithms used. It is shown that when jobs are switched, a substantial number of memory requests are required before the buffer fills and gives a high hit ratio. It is also shown that individuaIly buffered main-memory modules can be interleaved to achieve very high system performance.

Studies of cache store behaviour in a real-time minicomputer environment

Abstract: The letter reports simulation studies of cache storage in a real-time minicomputer environment. Direct mapping is shown to be the most effective approach to cache management and the speedup achieved is also seen to depend on the class of program. Speedup factors of more than 5:1 can be achieved with modest-sized cache stores and relatively simple hardware.

The connection of an associative pipeline with a cache memory.

Abstract: The paper describes a pipeline computer, the concept of which has been developed at the Institut fur Informatik at the Technical University of Munich. The first part describes the problems arising in a pipeline computer executing programs with conditional branch instructions, and gives proposals how to solve them. In the second part the connection of a cache-memory with a pipeline is discussed. Such a connection increases the number of instructions which are suited for advance execution.