Showing papers on "Cache coloring published in 2020"

The Potential of Programmable Logic in the Middle: Cache Bleaching

Abstract: Consolidating hard real-time systems onto modern multi-core Systems-on-Chip (SoC) is an open challenge. The extensive sharing of hardware resources at the memory hierarchy raises important unpredictability concerns. The problem is exacerbated as more computationally demanding workload is expected to be handled with real-time guarantees in next-generation Cyber-Physical Systems (CPS). A large body of works has approached the problem by proposing novel hardware redesigns, and by proposing software-only solutions to mitigate performance interference.Strong from the observation that unpredictability arises from a lack of fine-grained control over the behavior of shared hardware components, we outline a promising new resource management approach. We demonstrate that it is possible to introduce Programmable Logic In-the-Middle (PLIM) between a traditional multi-core processor and main memory. This provides the unique capability of manipulating individual memory transactions. We propose a proof-of-concept system implementation of PLIM modules on a commercial multi-core SoC. The PLIM approach is then leveraged to solve long-standing issues with cache coloring. Thanks to PLIM, colored sparse addresses can be re-compacted in main memory. This is the base principle behind the technique we call Cache Bleaching. We evaluate our design on real applications and propose hypervisor-level adaptations to showcase the potential of the PLIM approach.

Page Reusability-Based Cache Partitioning for Multi-Core Systems

Abstract: Most modern multi-core processors provide a shared last level cache (LLC) where data from all cores are placed to improve performance. However, this opens a new challenge for cache management, owing to cache pollution. With cache pollution, data with weak temporal locality can evict other data with strong temporal locality when both are mapped into the same cache set. In this article, we propose page reusability-based cache partitioning (PRCP) for multi-core systems to maximize cache utilization by minimizing cache pollution. To achieve this, PRCP divides pages into two groups: (1) highly-reused pages and (2) lowly-reused pages. The reusability of each page is collected online via periodic page table scans. PRCP then dynamically partitions the shared cache into two corresponding areas using page coloring technique. We have implemented PRCP in Linux kernel and evaluated it using SPEC CPU2006 benchmarks. The results show that our scheme can achieve comparable performance to the optimal offline MRC-guided process-based cache partitioning scheme without a priori knowledge of workloads.

L2 Cache Robust Partitioning in Multicore Processors

Abstract: Automotive and, especially, the aerospace industry requires reducing the size, weight, and power (SWaP) of the embedded electronics. Additionally, both industries demand an increment of the embedded electronics’ power capability and low data transfer latency. Multi-core processors’ (MCP) advent allows integrating multiple applications in the same System on Chip (SoC) in high-performance computers. The usage of MCP processor in safety-critical systems such as Flight Control Computers and Autonomous Driving depends on solving determinism issues related to the processor’s resource contention. The usage of a resource from one core can impact the other cores, preventing the delivery of the algorithm output at a specific time, and this failure can lead to a catastrophic event. This paper introduces an analysis of interference paths to map the possible resource contention in MCP and presents an approach to mitigate the low-level cache (LLC) contention using the page coloring technique.