Showing papers on "Cache invalidation published in 2021"
Posted Content•
TL;DR: In this paper, the privacy of the users' demands was taken into consideration, i.e., each user can only get its required file and can not get any information about the demands of other users.
Abstract: Recently Hachem et al. formulated a multiaccess coded caching model which consists of a central server connected to $K$ users via an error-free shared link, and $K$ cache-nodes. Each cache-node is equipped with a local cache and each user can access $L$ neighbouring cache-nodes with a cyclic wrap-around fashion. In this paper, we take the privacy of the users' demands into consideration, i.e., each user can only get its required file and can not get any information about the demands of other users. By storing some private keys at the cache-nodes, we propose a novel transformation approach to transform a non-private multiaccess coded caching scheme into a private multiaccess coded caching scheme.
3 citations
TL;DR: This research shall investigate the L1 cache, primary cache, and L2 cache as a secondary proxy server cache to anticipate the average period of usage of LRU, LRU_AVL, andLRU_BST cache algorithms.
2 citations
13 Jan 2021
TL;DR: In this article, the authors demonstrate a FLUSH+RELOAD attack on T table-based AES in unprivileged user mode using cache flush instruction on Arm processor through ACP.
Abstract: Cache side-channel attacks have been getting remarked as it threatens the information security of the multitenant systems. Among them, the FLUSH+RELOAD attack is one of the high-accuracy and high-resolution cache side-channel attacks. However, there have been few works targeting Arm architecture due to its architectural differences from x86 processors such as accessibility of cache flush instruction. In this paper, we design hardware that allows unprivileged cache invalidation on Arm processor through ACP. By utilizing the developed IP, we demonstrate a FLUSH+RELOAD attack on T table-based AES in unprivileged user mode. Our suggestion shows better performance than previous studies using cache flush instruction.
2 citations
Patent•
04 May 2021
TL;DR: In this paper, a memory system may include: a memory having a memory address space associated therewith to access the memory; a cache memory assigned to the memory, and one or more processors configured to generate a dummy address space in addition to the main address space.
Abstract: According to various aspects, a memory system may include: a memory having a memory address space associated therewith to access the memory; a cache memory assigned to the memory; one or more processors configured to generate a dummy address space in addition to the memory address space, each address of the dummy address space being distinct from any address of the memory address space, and generate one or more invalid cache entries in the cache memory, the one or more invalid cache entries referencing one or more dummy addresses of the dummy address space.