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Cache invalidation

About: Cache invalidation is a research topic. Over the lifetime, 10539 publications have been published within this topic receiving 245409 citations.


Papers
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Patent
John G. Aschoff1, Jeffrey A. Berger1, David Alan Burton1, Bruce McNutt1, Stanley C. Kurtz1 
19 May 1993
TL;DR: In this article, the authors allocate read cache space among bands of DASD cylinders rather than to data sets or processes as a function of a weighted average hit ratio to the counterpart cache space.
Abstract: Dynamic allocation of read cache space is allocated among bands of DASD cylinders rather than to data sets or processes as a function of a weighted average hit ratio to the counterpart cache space. Upon the hit ratio falling below a predetermined threshold, the bands are disabled for a defined interval as measured by cache accesses and then rebound to cache space again.

94 citations

Book ChapterDOI
25 Oct 2004
TL;DR: This paper proposes a different cache architecture, intended to ease WCET analysis, where the cache stores complete methods and cache misses occur only on method invocation and return.
Abstract: Cache memories are mandatory to bridge the growing gap between CPU speed and main memory access time. Standard cache organizations improve the average execution time but are difficult to predict for worst case execution time (WCET) analysis. This paper proposes a different cache architecture, intended to ease WCET analysis. The cache stores complete methods and cache misses occur only on method invocation and return. Cache block replacement depends on the call tree, instead of instruction addresses.

94 citations

Patent
Steven Paul Vanderwiel1
26 Oct 2005
TL;DR: In this paper, a selection mechanism selects lines evicted from the higher level cache for storage in the victim cache, only some of the evicted lines being selected for the victim.
Abstract: A computer system cache memory contains at least two levels. A lower level selective victim cache receives cache lines evicted from a higher level cache. A selection mechanism selects lines evicted from the higher level cache for storage in the victim cache, only some of the evicted lines being selected for the victim. Preferably, two priority bits associated with each cache line are used to select lines for the victim. The priority bits indicate whether the line has been re-referenced while in the higher level cache, and whether it has been reloaded after eviction from the higher level cache.

94 citations

Proceedings ArticleDOI
11 Apr 2011
TL;DR: A refined persistence analysis method is presented which fixes the potential underestimation problem in the original persistence analysis and a framework to combine access pattern analysis and abstract interpretation for accurate data cache analysis is proposed.
Abstract: Caches are widely used in modern computer systems to bridge the increasing gap between processor speed and memory access time. On the other hand, presence of caches, especially data caches, complicates the static worst case execution time (WCET) analysis. Access pattern analysis (e.g., cache miss equations) are applicable to only a specific class of programs, where all array accesses must have predictable access patterns. Abstract interpretation-based methods (must/persistence analysis) determines possible cache conflicts based on coarse-grained memory access information from address analysis, which usually leads to significantly pessimistic estimation. In this paper, we first present a refined persistence analysis method which fixes the potential underestimation problem in the original persistence analysis. Based on our new persistence analysis, we propose a framework to combine access pattern analysis and abstract interpretation for accurate data cache analysis. We capture the dynamic behavior of a memory access by computing its temporal scope (the loop iterations where a given memory block is accessed for a given data reference) during address analysis. Temporal scopes as well as loop hierarchy structure (the static scopes) are integrated and utilized to achieve a more precise abstract cache state modeling. Experimental results shows that our proposed analysis obtains up to 74% reduction in the WCET estimates compared to existing data cache analysis.

94 citations

Proceedings ArticleDOI
23 Mar 2004
TL;DR: A cache signature scheme is devised for COCA that provides hints for the mobile clients to determine whether a required data item is cached by their neighboring peers based on their local state, and is shown to be capable of effectively reducing the number of server requests and power consumption.
Abstract: Caching is a key technique for improving the data retrieval performance of mobile clients in mobile environments. The emergence of robust and reliable peer-to-peer (P2P) technologies now brings to reality what we call "cooperative caching " in which mobile clients can access data items from the cache in their neighboring peers. We discuss cooperative caching in mobile environments and proposes a cooperative caching scheme for mobile systems, called COCA. In COCA, we identify two types of mobile clients: low activity and high activity. They are referred to as low activity mobile client/host (LAM) and high activity mobile client/host (HAM) respectively. Both LAM and HAM can share their cache. The server replicates appropriate data items to LAMs so that HAMs can take advantages of the LAM replicas. The performance of pure COCA and COCA with the data replication scheme is evaluated through a number of simulated experiments which show that COCA significantly reduces both the server workload in terms of number of requests and the access miss ratio when the MHs reside outside of the service area. The COCA with the data replication scheme can improve the overall system performance in other aspects as well.

94 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202344
2022117
20214
20208
20197
201820