Cache invalidation

About: Cache invalidation is a research topic. Over the lifetime, 10539 publications have been published within this topic receiving 245409 citations.

Method and apparatus for injecting write data into a cache

Abstract: A data processing system (100, 600) has a memory hierarchy including a cache (124, 624) and a lower-level memory system (170, 650). A data element having a special write with inject attribute is received from a data producer (160, 640), such as an Ethernet controller. The data element is forwarded to the cache (124, 624) without accessing the lower-level memory system (170, 650). Subsequently at least one cache line containing the data element is updated in the cache (124, 624).

Pipeline having an integral cache which processes cache misses and loads data in parallel

Abstract: A load/store pipeline in a computer processor for loading data to registers and storing data from the registers has a cache memory within the pipeline for storing data. The pipeline includes buffers which support multiple outstanding read request misses. Data from out of the pipeline is obtained independently of the operation of the pipeline, this data corresponding to the request misses. The cache memory can then be filled with the data that has been requested. The provision of a cache memory within the pipeline, and the buffers for supporting the cache memory, speed up loading operations for the computer processor.

Method, system and program product for caching data objects

Abstract: Under the present invention, a history of requests for data objects are tracked and maintained in a cache log. Based on the history, certain data objects are prefetched into a cache. When a request for a cached data object is later received, the requested data object can be retrieved from the cache and served to the requesting user. Thus, the latency involved with obtaining the data objects from the appropriate sources is eliminated. Further, under the present invention, discard and refresh rules are assigned to each data object on a class basis. Accordingly, data objects in the cache can be refreshed and/or discarded so that the caching operation can be optimized.

A Server-Side Solution to Cache-Based Side-Channel Attacks in the Cloud

Abstract: As Cloud services become more common place, recent work have uncovered vulnerabilities unique to Cloud systems. Specifically, the paradigm promotes a risk of information leakage across virtual machine isolation via side-channels. In this paper, we investigate the current state of side-channel vulnerabilities involving the CPU cache, and identify the shortcomings of traditional defenses in a Cloud environment. We explore why solutions to non-Cloud cache-based side-channels cease to work in Cloud environments, and develop a mitigation technique applicable for Cloud security. Applying this solution to a canonical Cloud environment, we demonstrate the validity of this Cloud-specific, cache-based side-channel mitigation technique. Furthermore, we show that it can be implemented as a server-side approach to improve security without inconveniencing the client. Finally, we conduct a comparison of our solution to the current state-of-the-art.

Method and apparatus for controlling one or more hierarchical memories using a virtual storage scheme and physical to virtual address translation

Abstract: A processing apparatus of an integrated circuit structure for a multiprocessor system includes an execution unit operative on the basis of a virtual storage scheme and a cache memory having entries designated by logical addresses from the execution unit For controlling the cache memory, a first address array containing entries designated by the same logical addresses as the cache memory and storing control information for the corresponding entries of the cache memory is provided in association with a second address array having entries designated by physical addresses and storing translation information for translation of physical addresses to logical addresses for the entries When a physical address at which invalidation is to be performed is inputted in response to a cache memory invalidation request supplied externally, access is made to the second address array by using the physical address to obtain the translation information from the second address array to thereby generate a logical address to be invalidated The first address array is accessed by using the generated logical address to perform a invalidation processing on the control information