Showing papers on "Cache pollution published in 1985"

Memory back-up system

Abstract: Apparatus for maintaining duplicate copies of information stored in fault-tolerant computer main memories is disclosed. A non write-through cache memory associated with each of the system's processing elements stores computations generated by that processing element. At a context switch, the stored information is sequentially written to two separate main memory units. A separate status area in main memory is updated by the processing element both before and after each writing operation so that a fault occurring during data processing or during any storage operation leaves the system with sufficient information to be able to reconstruct the data without loss of integrity. To efficiently transfer information between the cache memory and the system main memories without consuming a large amount of processing time at context switches, a block status memory associated with the cache memory contains an entry for each data block in the cache memory. The entry indicates whether the corresponding data block has been modified during data processing or written with computational data from the processing element. The storage operations are carried out by high-speed hardware which stores only the modified data blocks. Additional special-purpose hardware simultaneously invalidates all cache memory entries so that a new task can be loaded and started.

Implementing a cache consistency protocol

Abstract: We present an ownership-based multiprocessor cache consistency protocol, designed for implementation by a single chip VLSI cache controller. The protocol and its VLSI realization are described in some data, to emphasize the important implementation issues, in particular, the controller critical sections and the inter- and intra-cache interlocks needed to maintain cache consistency. The design has been carried through to layout in a P-Well CMOS technology.

Disk cache—miss ratio analysis and design considerations

Abstract: The current trend of computer system technology is toward CPUs with rapidly increasing processing power and toward disk drives of rapidly increasing density, but with disk performance increasing very slowly if at all. The implication of these trends is that at some point the processing power of computer systems will be limited by the throughput of the input/output (I/O) system.A solution to this problem, which is described and evaluated in this paper, is disk cache. The idea is to buffer recently used portions of the disk address space in electronic storage. Empirically, it is shown that a large (e.g., 80-90 percent) fraction of all I/O requests are captured by a cache of an 8-Mbyte order-of-magnitude size for our workload sample. This paper considers a number of design parameters for such a cache (called cache disk or disk cache), including those that can be examined experimentally (cache location, cache size, migration algorithms, block sizes, etc.) and others (access time, bandwidth, multipathing, technology, consistency, error recovery, etc.) for which we have no relevant data or experiments. Consideration is given to both caches located in the I/O system, as with the storage controller, and those located in the CPU main memory. Experimental results are based on extensive trace-driven simulations using traces taken from three large IBM or IBM-compatible mainframe data processing installations. We find that disk cache is a powerful means of extending the performance limits of high-end computer systems.

Hierarchical cache memory system and method

Abstract: A caching system for a shared bus multiprocessor which includes several processors each having its own private cache memory. Each private cache is connected to a first bus to which a second, higher level cache memory is also connected. The second, higher level cache in turn is connected either to another bus and higher level cache memory or to main system memory through a global bus. Each higher level cache includes enough memory space so as to enable the higher level cache to have a copy of every memory location in the caches on the level immediately below it. In turn, main memory includes enough space for a copy of each memory location of the highest level of cache memories. The caching can be used with either write-through or write-deferred cache coherency management schemes.

Cache evaluation and the impact of workload choice

Abstract: The selection of the "best" parameters for a cache design, such as size, mapping algorithm, fetch algorithm, line size, etc., is dependent on the expected workload. Similarly, the machine performance is sensitive to the cache performance which itself depends on the workload. Most cache designers have been greatly handicapped in their designs by the lack of realistic cache performance estimates. Published research generally presents data which is unrealistic in some respects, and available traces are often not representative. In this paper, we present measurements from a very wide variety of traces: there are 49 traces, taken from G machine architectures, (370, 360, VAX, MG8000, Z8000, CDC 6400), coded in 7 source languages. Statistics are shown for miss ratios, the effectiveness of prefetching in terms of both miss ratio and its effect on bus traffic, the frequency of writes, reads and instruction fetches, and the frequency of branches. Some general observations are made and a "design estimate" set of miss ratios are proposed. Some "fudge" factors are proposed by which statistics for workloads for one machine architecture can be used to estimate corresponding parameters for another (as yet unrealized) architecture. 1. I n t r o d u c t i o n Almost all medium and high performance machines and most high performance microprocessors now being designed will include cache memories to be used for instructions, for data or for both. There are a number of choices to be made regarding the cache including size, line size (block size), mapping algorithm, replacement algorithm, writeback algorithm, split (instructions/data) vs. unified, fetch algorithm, et cetera; see [Smit82] for a detailed discussion of these issues. Making the "best" choices and selecting the *'best" parameters (with respect to cost and performance) depends greatly on the workload to be expected [Macd84]. For example, a cache which achieves a 99% hit ratio may cost 80% more than one which achieves 98%, may increase the CPU cost by 25°7o and may only boost overall CPU performance by 8%; that suggests that the higher performing cache is not cost effective. However, if the same two designs yield hit ratios of 90°70 and 80~ respectively, and if the performance increase would be 50~, then different conclusions might well be reached. Computer architects have been handicapped by the lack of generally available realistic cache workload estimates. *Tke material prtseated here i* bued on reJe~rck n p p o r t ~ ia part by the Nation*! Science Foundation under g n a t DCR-IU202591 and by tie Ddeue Ad*~nced Rele~rck Project; Agency ¢uder contract N000~9-82-CC,-¢235. Computer time 5 u been provided by tke Stanford Linear Accderatot Center nnder Department of EuerKy contract DEA@0~-?~hSF-00SIS. While there are hundreds of published papers on cache memories (see [Smit82] for a partial bibliography), only a few present usable data. A large fraction contain no measurements at all. Almost all of the papers that do present measurements rely on trace driven simulation using a small set of traces, and for reasons explained further below, those gra.:es are likely to be unrepresentative of the results to be expected in practice. There do exist some realistic numbers, as we note below, but they are hardly enough to constitute a design database. The purpose of this paper is discuss and explain workload selection as it relates to cache memory design, and to present data from which the designer can work. We have used 49 program address traces taken from 0 (or 5, if the 300 and 370 are the same) machine architectures (VAX, 370, 300/91, Z8000, CDC 0400, M08000), derived from 7 programming languages (Fortran, 370 Assembler, APL, C, LISP, AlgolW, Cobol) to compute overall, instruction and data miss ratios and bus traffic rates for various cache designs; these experiments show the variety of workload behavior possible. Characteristics of the traces are tabulated and the effects of some design choices are evaluated. Finally, we present what we consider to be a "re~onable" set of numbers with which we believe designers can comfortably work. In that discussion, we also suggest some "fudge" factors, which indicate how realistic (or available) number~ for machine architecture MI under workload conditions W1 can be used to estimate similar parameters for architecture M2 under workload WI*. In the remainder of this section, we discuss additional background for our measurement results. First we consider the advantages and disadvantages of trace driven simulation. Then we review some {possible) eases of performanee misprediction and also discuss some published and valid miss ratio figures. The second section discusees the traces used. The measurement results and analysis are in section 3, and in section 4 we propose target workload values and factors by which one workload can be used to estimate another. Section 5 summarizes our findings. 1.1 . T r a c e Dr iven Simula t ion A p r o g r a m a d d r e n t race is a trace of the sequence of (virtual) addresses accessed by a computer program or programs. T r a c e dr iven l imul&tlon involves driving a simulation model of a system with a trace of external stimuli rather than with a random number generator. Trace driven simulation is a very good way to study many aspects of cache design and performance, for a number of reasons. First, it is superior to either pure mathematical models or random number driven simulation because there do not currently exist any generally accepted or believable models for those characteristics of program behavior that determine cache performance; thus it is not possible to specify a realistic model nor to drive a simulator with a good representation of a program. A trace properly 0149-7111/85/0000/0064501.00 © 1985 IEEE 64 represents at least one real program, and in certain respects can be expected to drive the simulator correctly. It is important to note that a trace reflects not only the program traced and the functional architecture of the machine (instruction set) but also the design a r c h i t e c t u r e (higher level implementation). In particular, t h e n u m b e r o f m e m o r y references k affected by the width o f the data path to memory : fetching two four-byte instructions requires 4, 2 or 1 memory reference, depending on whether the memory interface is 2, 4 or 8 bytes wide. It also depends on how much "memory" the interface itself has; if one request is for 4 bytes, the next request is for the next four bytes, and the interface is 8 bytes wide, then fewer fetches will result if the interface "remembers" that it has the target four bytes of the second fetch rather than redoing the fetch. The interface can be quite complex, as with the lfetch buffer in the VAX 11/780 [Clar83] and can behave differently for instructions and data. (A trace should reflect, to the greatest possible extent, only the functional architecture; the design architecture should and usually can be emulated in the simulator.) A simulator is also much better in many ways than the construction of prototype designs. It is far faster to build a simulator, and the design being simulated can be varied easily, sometimes by just changing an input parameter. Conversely, a hardware prototype can require man-years to build and can be varied little if at all. Also, the results of a live workload tend to yield slightly different results (e.g. 1% to 3%) from run to run, depending on the random setting of initial conditions such as the angular position of the disks [Curt75]. For the reasons given above, trace driven simulation has been used for almost every research paper which presents cache measurements, with a few exceptions discussed below. There are, however, several reasons why the results of trace driven simulations should be taken with a grain of salt. (1) A trace driven simulation of a million memory addresses, which is fairly long, represents about 1/30 of a second for a machine such as the IBM 3081, and only about one second for an M68000; thus a trace is only a very small sample of a real workload. (2) Traces seldom are taken from the "messiest" parts of large programs; more often they are traces of the initial portions of small programs. (3) It is very difficult to trace the operating system (OS) and few OS traces are available. On many machines, however, the OS dominates the workload. (4) Most real machines task switch every few thousand instructions and are constantly taking interrupts. It is difficult to include this effect accurately in a trace driven simulation and many simulators don't try. (5) The sequence of memory addresses presented to the cache can vary with hardware buffers such ~ prefetch buffers and loop buffers, and is certainly sensitive to the data path width. Thus the trace itself may not be completely accurate with ree.pect to the implementation of the architecture. (0) In running machines, a certain (usually small) fraction of the cache activity is due to input/output; this effect is seldom included in trace driven simulations. In this paper we are primarily concerned with items 1-3 immediately above. By presenting the results of a very large number of simulations, one can get an idea of the range of program behavior. Included are two traces of IBM's MVS operating system, which should have performance that is close to the worst likely to be observed. 1.2. Rea l W o r k l o a d s and Ques t ionab le Estlmattm There arc only a small number of papers in which provide measurements taken by hardware monitors from running machines. In [Mila75] it is reported that a 16K cache on an IBM 370/105-2 running VS2 had a 0.94 hit ratio, with 1.6 fetches per instruction and .22 stores/instruction; it is also found that 73% of the CPU cycles were used in supervisor state. Merrill [Merr74] found cache hit ratios for a 16K cache in the 370/168 of 0.932 to 0.997 for six applications programs, and also reports that the performance (MI

Instruction Cache Replacement Policies and Organizations

Abstract: Instruction cache replacement policies and organizations are analyzed both theoretically and experimentally. Theoretical analyses are based on a new model for cache references —the loop model. First the loop model is used to study replacement policies and cache organizations. It is concluded theoretically that random replacement is better than LRU and FIFO, and that under certain circumstances, a direct-mapped or set-associative cache may perform better than a full-associative cache organization. Experimental results using instruction trace data are then given and analyzed. The experimental results indicate that the loop model provides a good explanation for observed cache performance.

Virtual cache system using page level number generating CAM to access other memories for processing requests relating to a page

Abstract: A multiprocessor computer system includes a main memory and a plurality of central processing units (CPU's) which are connected to share main memory via a common bus network. Each CPU has instruction and data cache units, each organized on a page basis for complete operating compatibility with user processes. Each cache unit includes a number of content addressable memories (CAM's) and directly addressable memories (RAM's) organized to combine associative and direct mapping of data or instructions on a page basis. An input CAM in response to a CPU address provides a cache address which includes a page level number for identifying where all of the required information resides in the other memories for processing requests relating to the page. This organization permits the processing of either virtual or physical addresses with improved speed and reduced complexity and the ability to detect and eliminate both consistency and synonym problems.

Cache hierarchy design for use in a memory management unit

Abstract: A cache hierarchy to be managed by a memory management unit (MMU) combines the advantages of logical and virtual address caches by providing a cache hierarchy having a logical address cache backed up by a virtual address cache to achieve the performance advantage of a large logical address cache, and the flexibility and efficient use of cache capacity of a large virtual address cache. A physically small logical address cache is combined with a large virtual address cache. The provision of a logical address cache enables reference count management to be done completely by the controller of the virtual address cache and the memory management processor in the MMU. Since the controller of the logical address cache is not involved in the overhead associated with reference counting, higher performance is accomplished as the CPU-MMU interface is released as soon as the access to the logical address cache is completed.

Simplified cache with automatic update

Abstract: A simplified cache with automatic updating for use in a memory system. The cache and the main memory receive data from a common input, and when a memory write operation is performed on data stored at a memory location for which there is a corresponding cache location, the data is written simultaneously to the cache and to the main memory. Since a cache location coresponding to a memory location always contains a copy of the data at the memory location, there is no need for dirty bits or valid bits in the cache resisters and the associated logic in the cache control. The main memory used with the invention may receive data either from a CPU or from I/O devices, and the cache includes apparatus permitting the CPU to perform cache read operations while the main memory is receiving data from an I/O device.

Cache memory architecture for microcomputer speed-up board

Abstract: A method and apparatus for enhancing the speed of operation of a computer consists of providing a cache memory which is faster than the computer's main memory, disabling the computer's main microprocessor, and replacing it with a microprocessor with a faster clock cycle time. A portion of the program stored in the main memory is stored in the cache memory. The addresses of the portion of the main memory stored in the cache memory are noted in a tag RAM. Upon each addressing sequence during the execution of a program, the tag RAM is examined to determine if the addressed located is stored in the cache memory. If the stored location is identified in the tag RAM, it is retrieved from the cache memory at high-speed. Otherwise, the data in the address location is retrieved from main memory at a slower speed and written into the cache memory so that subsequent accesses may be made at high-speed.

I/o controller for multiple disparate serial memories with a cache

Abstract: An I/O controller for a computer system having a plurality of memory devices of different types such as floppy and hard disks, whereinn a single cache memory is employed for all of the memory devices. Each of the memory devices is provided with its own interface device which directs data outputted from the associated memory device onto a common device bus. From the device bus data is transferred to a cache memory via a separate cache bus, and then to a system processor via the same cache bus. Memory space within the cache memory may be allocated among the various memory devices.

Cache memory address apparatus

Abstract: In a processor system with a virtual memory organization and a cache memory table storing the physical addresses corresponding to the most-recenty used virtual addresses, access to the cache table is enhanced by associating upper and lower MSB portions of a virtual address with corresponding upper and lower portions of an associated cache address. The separate cache address portions are placed in separate cache address storage devices. Each cache address storage device is addressed by respective virtual address MSB portions. A physical address storage device stores physical addresses translated from virtual addresses in storage locations addressed by cache addresses associated with the respective virtual addresses from which the physical addresses were translated.

Variable segment size plural cache system with cache memory unit selection based on relative priorities of accessed encached programs

Abstract: A cache memory control system has a segment descriptor with a 1-bit cache memory unit designation field, and a register for storing data representing the cache memory unit designation field. An output from the register is supplied to one cache memory unit, whereas inverted data of the output from the register is supplied to the other cache memory unit.

Virtually addressed caches for multiprogramming and multiprocessing environments

Abstract: Virtually addressed caches offer advantages of improved performance and simplicity of design over real addressed caches. They have not been generally used because their implementation presents some difficulties. A technique was devised to allow the use of virtually addressed cache by multiple processes sharing global memory without cache coherency problems. When the question of how to best combine I/O subsystems with virtually addressed cache using that technique was raised, several more problems were discovered. These included the MMU coherency problem and the question of whether the MMU should be associated with the processor or with main memory. The advantages and disadvantages of a large number of locations of processors, caches, buses, MMUs, and main memories were discussed. Associating the MMU(s) with main memory rather than with the cache or the processor has a number of advantages. These advantages include a solution to the MMU coherency problem, better performance, virtual addresses for I/O which yields uniform addresses for all references, and simplicity of design. An implementation of the ideas developed in this dissertation is proposed. The system to be implemented is a multiprocessor workstation using shared global memory for multiprocessing and multiprogramming tasks. Operating system and system software issues are discussed. In the uniprocessor case, the expected performance gain due to using virtually addressed cache is significant, primarily because it allows non-paged address translation units to be used. Comparisons were made between real address cache architectures and virtual address cache architectures. In the multiprocessor case, there is also a gain in performance for all of the reasons which apply with uniprocessors, plus a reduction in bus contention. There is also a considerable reduction in the complexity of the system. All of the processors, including I/O processors, can be treated in a uniform fashion with respect to the protocol for memory access. Each processor deals with virtual addresses only. Translation of virtual addresses is defered until a main memory reference occurs. The main memory translates the virual address to a real address, maintains cache coherency between the various processors, detects page faults, and transfers data.

Data processing system which selectively bypasses a cache memory in fetching information based upon bit information of an instruction

Abstract: A cache memory contained in a processor features a high efficiency in spite of its small capacity. In the cache memory control circuit, it is detected whether the access operation of the processor is directed to a particular region of the memory, and when the data is to be read out from, or is to be written onto, the particular region, the data is copied onto the cache memory and when the data is to be read out from other regions, operation of the memory is executed immediately without waiting for the reference of cache memory. By assigning the particular region for the data that is to be used repeatedly, it is possible to provide a cache memory having good efficiency in spite of its small capacity. A representative example of such data is the data in a stack.

Multiprocessor shared pipeline cache memory

Abstract: A cache memory unit is constructed to have a two-stage pipeline shareable by a plurality of sources which include two independently operated central processing units (CPUs). Apparatus included within the cache memory unit operates to allocate alternate time slots to the two CPUs which offset their operations by a pipeline stage. This permits one pipeline stage of the cache memory unit to perform a directory search for one CPU while the other pipeline stage performs a data buffer read for the other CPU. Each CPU is programmed to use less than all of the time slots allocated to it. Thus, the processing units operate conflict-free while pipeline stages are freed up for processing requests from other sources, such as replacement data from main memory or cache updates.

Optimal prepaging and font caching

Abstract: An efficient algorithm for communicating letter-shape information from a high-speed computer with a large memory to a typesetting device that has a limited memory is presented. The encoding is optimum, in the sense that the total time for typesetting is minimized, using a model that generalizes well-known “demand paging” strategies to the case where changes to the cache are allowed before the associated information is actually needed. Extensive empirical data show that good results are obtained even when difficult technical material is being typeset on a machine that can store information concerning only 100 characters. The methods of this paper are also applicable to other hardware and software caching applications with restricted lookahead.

Cache memory control circuit

Abstract: A cache memory (26) is contained in a processor (1) which features a high efficiency in spite of its small capacity. In the cache memory control circuit of the invention, it is detected whether the access operation of the processor is directed to a particular region of the memory, and when the data is to be read out from, or is to be written onto, the particular region, the data is copied onto the cache memory (26) and when the data is to be read out from other regions, operation of the memory is executed immediately without waiting for the reference of cache memory. By assigning the particular region for the data that are to be used repeatedly, it is possible to obtain a cache memory (26) having good efficiency in spite of its small capacity. A representative example of such data is the data in a stack.

High-speed buffer store arrangement for fast transfer of data

Abstract: In a data processing system comprising multiple cache buffer stores (17, 19) in a hierarchical arrangement, fast transfer of wide data blocks is enabled by particular cache configurations and cache interconnections. On each cache chip, input and output (39, 45) latches are integrated thus avoiding separate intermediate buffering. Input and output latches are interconnected by 64-byte wide data buses (B, A'; D, A") so that data blocks can be shifted rapidly from one cache hierarchy level to another and back. Chip-internal feedback connections from output to input latches allow to selectively reenter data blocks into a cache after reading. An additional register array (47) is provided so that data blocks after transfer from a cache to main memory or CPU can be subsequently furnished again without accessing the respective cache. The disclosed system allows to transfer wide data blocks within one cycle, thus tying-up caches much less in transfer operations, so that their availability is increased.

Cache-effective sort string generation method

Abstract: A new use for an LRU-managed cache coupling the main memory of a CPU for sort string generation of m records while minimizing the number of reference misses per record to said cache is described. During a first pass, a partially nested ordering or sort is effectuated using the cache, and then during a second pass a replacement selection merge upon the nested order constrained to fit within the cache is brought about.

Working set prefetch for level two caches

Abstract: WORKING SET PREFETCH FOR LEVEL TWO CACHES Abstract In a computing system including a three level memory hierarchy comprised of a first level cache (L1), a second level cache (L2) and a main memory (L3), a working set history table is included which keeps a record of which lines in an L2 block where utilized when resident in the L2 cache through the use of tags. When this L2 block is returned to main memory and is subsequently requested, only the lines which were utilized in the last residency are transferred to the L2 cache. That is, there is a tag for future use of a line based on its prior use during its last residency in the L2 cache.

Cache coherence system

Abstract: A cache coherence system for a multiprocessor system including a plurality of data processors coupled to a common main memory. Each of the data processors includes an associated cache memory having storage locations therein corresponding to storage locations in the main memory. The cache coherence system for a data processor includes a cache invalidate table (CIT) memory having internal storage locations corresponding to locations in the cache memory of the data processor. The cache coherence system detects when the contents of storage locations in the cache memories of the one or more of the data processors have been modified in conjunction with the activity those data processors and is responsive to such detections to generate and store in its CIT memory a multiple element linked list defining the locations in the cache memories of the data processors having modified contents. Each element of the list defines one of those cache storage locations and also identifies the location in the CIT memory of the next element in the list.

Memory Hierarchy Aspects of a Multiprocessor RISC: Cache and Bus Analyses

Abstract: We describe the memory system design of a tightly-coupled multiprocessor. Each processor node consists of a VLSI RISC processor, a VLSI cache controller, cache data RAMs, and a standard bus. We show that adequate performance can be achieved only if the processor has an on-chip instruction buffer and a large (64KB-256KB) local instruction and data cache. Ways of reducing the number of cache tags and the effects of various implementation alternatives for where to perform virtual memory translation are also described.

Computing system and method providing working set prefetch for level two caches

Abstract: In a computing system including a three level memory hierarchy comprised of a first level cache (L1), a second level cache (L2) and a main memory (L3), a working set history table is included which keeps a record of which lines in an L2 block where utilised when resident in the L2 cache through the use of tags. When this L2 block, or the material part thereof, is returned to main memory and is subsequently requested, only the lines which were utilised in the last residency are transferred to the L2 cache. That is, there is a tag for future use of a line based on its prior use during its last residency in the L2 cache.

Microcomputer memory and method for its operation

Abstract: @ A microcomputer memory system is organized into a plurality of banks (12). Each bank consists of an array of static column mode dynamic random access memories (DRAMs) of the type having an on-chip static buffer for storing an entire row. The static buffers associated with each bank functions as a distributed cache (24) to hold the last accessed row for the associated bank. A memory controller (18) receives real addresses from CPU (10) or other device on the memory bus (14) and extracts bank and row numbers from the address. The memory controller determines whether the accessed row for a memory bank is in the distributed cache and, if it is, accesses the distributed cache for that bank. Otherwise, the memory controller switches the contents of the distributed cache with the contents of the addressed row for that bank.

Some Aspects of the Dynamic Behavior of Hierarchical Memories

Abstract: In a computer system with a cache memory, the cache is effectively empty following a job switch, leading to a low hit rate and consequently lowered performance until the cache becomes reasonably full. The analysis shows that a job must run for several milliseconds before the average performance approaches that expected from a steady-state analysis. Care may therefore be needed in designing memory systems which have very high page-fault rates from main memory, or which include many levels in the memory hierarchy.

Pipelined processor having dual cache memories

Abstract: A pipelined digital computer processor system (10, Figure 1) is provided comprising an instruction prefetch unit (IPU, 2) for prefetching instructions and an arithmetic logic processing unit (ALPU, 4) for executing instructions. The IPU (2) has associated with it a high speed instruction cache (6), and the ALPU (4) has associated with it a high speed operand cache (8). Each cache comprises a data store (84, 94, Figure 3) for storing frequently accessed data, and a tag store (82, 92, Figure 3) for indicating which main memory locations are contained in the respective cache. The IPU and ALPU processing units (2, 4) may access their associated caches independently under most conditions. When the ALPU performs a write operation to main memory, it also updates the corresponding data in the operand cache and, if contained therein, in the instruction cache. The IPU does not write to either cache. Provision is made for clearing the caches on certain conditions when their contents become invalid.