Cache pollution

About: Cache pollution is a research topic. Over the lifetime, 11353 publications have been published within this topic receiving 262139 citations.

A fully associative, tagless DRAM cache

Abstract: This paper introduces a tagless cache architecture for large in-package DRAM caches. The conventional die-stacked DRAM cache has both a TLB and a cache tag array, which are responsible for virtual-to-physical and physical-to-cache address translation, respectively. We propose to align the granularity of caching with OS page size and take a unified approach to address translation and cache tag management. To this end, we introduce cache-map TLB (cTLB), which stores virtual-to-cache, instead of virtual-to-physical, address mappings. At a TLB miss, the TLB miss handler allocates the requested block into the cache if it is not cached yet, and updates both the page table and cTLB with the virtual-to-cache address mapping. Assuming the availability of large in-package DRAM caches, this ensures that an access to the memory region within the TLB reach always hits in the cache with low hit latency since a TLB access immediately returns the exact location of the requested block in the cache, hence saving a tag-checking operation. The remaining cache space is used as victim cache for memory pages that are recently evicted from cTLB. By completely eliminating data structures for cache tag management, from either on-die SRAM or in-package DRAM, the proposed DRAM cache achieves best scalability and hit latency, while maintaining high hit rate of a fully associative cache. Our evaluation with 3D Through-Silicon Via (TSV)-based in-package DRAM demonstrates that the proposed cache improves the IPC and energy efficiency by 30.9% and 39.5%, respectively, compared to the baseline with no DRAM cache. These numbers translate to 4.3% and 23.8% improvements over an impractical SRAM-tag cache requiring megabytes of on-die SRAM storage, due to low hit latency and zero energy waste for cache tags.

Computer apparatus and method for caching results of a database query

Abstract: A query processor caches data retrieved from executing prepared statements, and uses the cached data for subsequent accesses to the data, if certain conditions for using the cached data are met. The preferred embodiments also include a data staleness handler that takes care of issues that arise from data that may have changed in the database but is not reflected in the cache. One way to handle data staleness in the cache is to specifically enable or disable caching in a query. If caching is disabled, the query processor will access the data in the database. Another way to handle data staleness in the cache is to provide a timer that causes the cache to be invalidated when the timer times out. Yet another way to handle data staleness in the cache is to provide specified conditions that must be met for caching to occur, such as time or date limitations. Still another way to handle data staleness in the cache is to provide an update trigger for the data in the database that corresponds to the cached data. When the data in the database is updated, the update trigger fires, causing the cache to be invalidated. Note that invalidating the cache could also be followed by automatically updating the cache. By caching the results of processing a prepared statement, other queries that use the same prepared statement may be able to access data in the cache instead of going to the database.

History table for set prediction for accessing a set associative cache

Abstract: A cache control maintains a history table SETLAT for the prediction of line entry (i.e., set member) within a congruence class for cache accessing. For a given cache access, a SETLAT entry can be selected based on the requesting logical address bits directly. The selection of a SETLAT entry may also be based on the hashing of such logical address bits together with other information in order to achieve sufficient randomization. A similar hashing history table may be devised to predict virtual address translation information with high accuracy. Such prediction mechanisms not only allow efficient implementation of the cache access path but also offer the opportunity of achieving multiple accesses per cycle. The proposed prediction method also provides a generic approach to efficient implementations for various directory based table accesses.

Decoupled compressed cache: exploiting spatial locality for energy-optimized compressed caching

Abstract: In multicore processor systems, last-level caches (LLCs) play a crucial role in reducing system energy by i) filtering out expensive accesses to main memory and ii) reducing the time spent executing in high-power states. Cache compression can increase effective cache capacity and reduce misses, improve performance, and potentially reduce system energy. However, previous compressed cache designs have demonstrated only limited benefits due to internal fragmentation and limited tags. In this paper, we propose the Decoupled Compressed Cache (DCC), which exploits spatial locality to improve both the performance and energy-efficiency of cache compression. DCC uses decoupled super-blocks and non-contiguous sub-block allocation to decrease tag overhead without increasing internal fragmentation. Non-contiguous sub-blocks also eliminate the need for energy-expensive re-compaction when a block's size changes. Compared to earlier compressed caches, DCC increases normalized effective capacity to a maximum of 4 and an average of 2.2 for a wide range of workloads. A further optimized Co-DCC (Co-Compacted DCC) design improves the average normalized effective capacity to 2.6 by co-compacting the compressed blocks in a super-block. Our simulations show that DCC nearly doubles the benefits of previous compressed caches with similar area overhead. We also demonstrate a practical DCC design based on a recent commercial LLC design.

System, apparatus, and method providing cache data mirroring to a data storage system

Abstract: The invention provides a system structure, method and computer program product for mirroring cache data from a first controller to an alternate controller in a data storage system, where the data storage system is being managed by the controllers in dual active configuration and the first and alternate controllers are also connected to a system drive that includes one or more disk storage devices and the first controller is connected to a first memory, and the alternate controller is connected to a second memory where each controller has an identical memory layout, and a cache line descriptor data structure defined therein and the cache line descriptor data structure is used by each respective controller to track data mirrored by the controller to a memory connected to an alternate controller and the cache line descriptor data structure includes information for reducing the amount of data mirrored to an alternate controller for secondary cache data mirror operations on same originating cache data with respect to a particular cache line and additionally, the cache line descriptor data structure includes information for coalescing multiple cache data mirror operations corresponding to a particular cache line into a single cache mirror operation to the alternate controller.