Cache pollution

About: Cache pollution is a research topic. Over the lifetime, 11353 publications have been published within this topic receiving 262139 citations.

How secure is your cache against side-channel attacks?

Abstract: Security-critical data can leak through very unexpected side channels, making side-channel attacks very dangerous threats to information security. Of these, cache-based side-channel attacks are some of the most problematic. This is because caches are essential for the performance of modern computers, but an intrinsic property of all caches – the different access times for cache hits and misses – is the property exploited to leak information in time-based cache side-channel attacks. Recently, different secure cache architectures have been proposed to defend against these attacks. However, we do not have a reliable method for evaluating a cache’s resilience against different classes of cache side-channel attacks, which is the goal of this paper.We first propose a novel probabilistic information flow graph (PIFG) to model the interaction between the victim program, the attacker program and the cache architecture. From this model, we derive a new metric, the Probability of Attack Success (PAS), which gives a quantitative measure for evaluating a cache’s resilience against a given class of cache side-channel attacks. We show the generality of our model and metric by applying them to evaluate nine different cache architectures against all four classes of cache side-channel attacks. Our new methodology, model and metric can help verify the security provided by different proposed secure cache architectures, and compare them in terms of their resilience to cache side-channel attacks, without the need for simulation or taping out a chip.CCS CONCEPTS• Security and privacy $\rightarrow $ Side-channel analysis and counter-measures; • General and reference $\rightarrow$ Evaluation; • Computer systems organization $\rightarrow $ Processors and memory architectures;

Optimization of cache evictions through software hints

Abstract: Program instructions permit software management of a processor cache. The program instructions may permit a software designer to provide software deallocation hints identifying data that is not likely to be used during further program execution. The program instructions may permit a processor to evict the identified data from a cache ahead of other eviction candidates that are likely to be used during further program execution. Thus, these software hints provide for better use of cache memory.

Apparatus and method for maintaining cache memory integrity in a shared memory environment

Abstract: A data processing system having a plurality of processors and a plurality of dedicated and shared memory modules. Each processor includes a cache for speeding up data transfers between the processor and its dedicated memory and also between the processor and one or more shared memories. The integrity of the data in each cache with respect to the shared memory modules is maintained by providing each shared memory with a cache monitoring and control capability which monitors processor reading and writing requests and, in response to this monitoring, maintains an accurate, updatable record of the data addresses in each cache while also providing for invalidating data in a cache when it is no longer valid.

Verifying a multiprocessor cache controller using random case generation

Abstract: The newest generation of cache controller chips provide coherency to support multiprocessor systems, i.e., the controllers coordinate access to the cache memories to guarantee a single global view of memory. The cache coherency protocols they implement complicate the controller design, making design verification difficult. In the design of the cache controller for SPUR, a shared memory multiprocessor designed and built at U.C. Berkeley, the authors developed a random tester to generate and verify the complex interactions between multiple processors in the the functional simulation. Replacing the CPU model, the tester generates memory references by randomly selecting from a script of actions and checks. The checks verify correct completion of their corresponding actions. The tester was easy to develop, and detected over half of the functional bugs uncovered during simulation. They used an assembly language version of the random tester to verify the prototype hardware. A multiprocessor system is operational; it runs the Sprite operating system and is being used for experiments in parallel programming.

Non-volatile backup for data cache

Abstract: A non-volatile data cache having a cache memory coupled to an external power source and operable to cache data of an external data device such that access requests for the data can be serviced by the cache rather than the external device. A non-volatile data storage device is coupled to the cache memory. An uninterruptible power supply (UPS) is coupled to the cache memory and the non-volatile data storage device so as to maintain the cache memory and the non-volatile storage device in an operational state for a period of time in the event of an interruption in the external power source.