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Cache pollution

About: Cache pollution is a research topic. Over the lifetime, 11353 publications have been published within this topic receiving 262139 citations.


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Patent
06 Aug 2002
TL;DR: In this article, a multi-proxy cache server supports unified forward and reverse proxy caching at a network edge of a defined content access domain, and includes a memory cache, supporting storage and access to forward proxy data and first reverse proxy data, and a disk cache supporting storage, access, and retrieval of second reverse proxies.
Abstract: A multi-proxy cache server supports unified forward and reverse proxy caching at a network edge of a defined content access domain. The multi-proxy cache server includes a memory cache, supporting storage and access to forward proxy data and first reverse proxy data, and a disk cache, supporting storage and access to second reverse proxy data. A controller, coupled to the memory cache and the disk cache, operates to retrieve, store and access content and further to receive and evaluate a content specification defining a plurality of content partitions for the respective preferential storage of a plurality of reverse proxy data sets.

62 citations

Patent
07 Oct 1999
TL;DR: In this article, a fail-over status bit in cache memory controller indicates when a cache line of the cache memory contains failover information from the defective or failing main memory so that that cache-line will not be written over by a cache replacement algorithm.
Abstract: A computer system having a main memory and a cache memory, the computer system uses portions of the cache memory to store information from defective main memory locations until the main memory can be repaired. The address space of the main memory is always maintained by substituting cache-lines of cache memory for the defective main memory locations. A fail-over memory status bit in the cache memory controller indicates when a cache line of the cache memory contains fail-over information from the defective or failing main memory so that that cache-line will not be written over by a cache replacement algorithm. When the fail-over status bit is set, the contents of the fail-over memory location(s) remains in the cache-line and all memory reads and writes are directed to only that cache-line of the cache memory and not the main memory for the fail-over memory location(s). Also no write-back of the fail-over memory location(s) from cache memory to the main memory is required nor desired until the main memory location is repaired or replaced. Indicator lights may be used to represent the different activities of the main and cache memories at detection of the defective memory location, during and after fail-over from the main memory location to the cache-line, and transfer back to the main memory once repaired. A plurality of cache memories may migrate fail-over information therebetween.

62 citations

Patent
04 Oct 1990
TL;DR: A checkpoint retry system for recovery from an error condition in a multiprocessor type central processing unit which may have a store-in or store-through cache system is presented in this paper.
Abstract: A checkpoint retry system for recovery from an error condition in a multiprocessor type central processing unit which may have a store-in or a store-through cache system. At detection of a checkpoint instruction, the system initiates action to save the content of the program status word, the floating point registers, the access registers and the general purpose registers until the store operations are completed for the checkpointed sequence. For processors which have a store-in cache, modified cache data is saved in a store buffer until the checkpointed instructions are completed and then written to a cache which is accessible to other processors in the system. For processors which utilize store-through cache, the modified data for the checkpointed instructions is also stored in the store buffer prior to storage in the system memory.

62 citations

Journal ArticleDOI
TL;DR: This article provides a survey on static cache analysis for real-time systems, presenting the challenges and static analysis techniques for independent programs with respect to different cache features, followed by a survey of existing tools based on static techniques for cache analysis.
Abstract: Real-time systems are reactive computer systems that must produce their reaction to a stimulus within given time bounds. A vital verification requirement is to estimate the Worst-Case Execution Time (WCET) of programs. These estimates are then used to predict the timing behavior of the overall system. The execution time of a program heavily depends on the underlying hardware, among which cache has the biggest influence. Analyzing cache behavior is very challenging due to the versatile cache features and complex execution environment. This article provides a survey on static cache analysis for real-time systems. We first present the challenges and static analysis techniques for independent programs with respect to different cache features. Then, the discussion is extended to cache analysis in complex execution environment, followed by a survey of existing tools based on static techniques for cache analysis. An outlook for future research is provided at last.

62 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202342
2022110
202112
202020
201915
201830