Showing papers on "Capacitance published in 1972"

Interface states in SiSiO2 interfaces

Abstract: Interface state parameters were studied in MOS capacitors over a wide range of energy by conductance and capacitance measurements at various temperatures from room temperature to liquid nitrogen temperature. A new technique was developed for analysis of the data which allows to obtain the density of states, the capture cross section, the surface potential and the dispersion parameter from the conductance and capacitance vs. frequency curves. The density of interface states as well as the electron capture cross section were found to be a function of energy only and to be independent of temperature. Maxima in the density of states have not been found.

Impurity centers in PN junctions determined from shifts in the thermally stimulated current and capacitance response with heating rate

Abstract: A theory is developed for the thermal response of pn junction current and capacitance where the junction contains deep impurity centers. Measurements lead to values for the energy level, emission coefficient and concentration of these centers. Energy levels and emission coefficients are found from shifts in either the current maxima or the capacitance slope maxima with heating rate. The theory indicates that the heating rate may be non-linear and that energy levels may be found independent of the emission coefficient. The analysis accounts for the possibility that only a portion of the space-charge region may contain charged deep centers. This allows the identification of centers in a small segment of the space-charge region. In addition, the analysis allows for the motion of the space-charge width as deep centers discharge. A gold-doped silicon n + p junction is used to verify the theory. The experimental hole emission parameters for the gold donor are in good agreement with those values obtained by other workers using different methods.

Optimum Snubbers for Power Semiconductors

Abstract: It is generally necessary to connect an RC snubber across a power rectifier or thyristor to absorb the energy associated with the recovery current of the device and limit the resulting voltage spike and rate of rise dv/dt. For a given snubber capacitance, it is shown that there is an optimum damping resistance which minimizes the peak voltage, but a lower resistance is required to minimize the average dv/dt to the peak. Design procedures are derived for selecting the capacitance and optimum resistance to limit the peak voltage or dv/dt to specified values. The device recovery current is trapped in circuit inductance, and its energy must be dissipated, while the snubber produces additional losses as the price of performing its limiting function.

Equivalent Capacitances of Microstrip Open Circuits

Abstract: The integral equations that describe the charge distribution near an open-circuited microstrip end are formulated and subsequently solved by a projective method. The solution hinges on development of computationally efficient techniques for dealing with the singularities that occur by special quadrature formulas. The necessary formulas are described and tabulated. These techniques are then used to find open-circuit capacitance values for microstrip. It is found that the curves of excess capacitance versus width are easily describable by empirical equations; such equations are presented, along with the curves themselves. For strip widths between 0.1 and 10 times the substrate thickness and for dielectric constants in the range 1-51, the given data are believed accurate to within a few percent.

Design of micron MOS switching devices

Abstract: Modern photolithographic technology offers the capability of fabricating MOSFET devices of micron dimensions and less. It is by no means obvious that such small devices can be designed with suitable electrical characteristics for LSI switchivg applications. In this talk we will describe short-channel devices ( L_{eff} \sim 1 µ) designed by scaling down larger devices with desirable electrical characteristics. Lateral and vertical dimensions, doping level, and operating voltages and currents are scaled in a self-consistent fashion. In this way small devices have been fabricated without the usual deleterious effects associated with short channels. The measured characteristics of these short-channel devices and the larger devices from which they were scaled will be compared.

Storage array and sense/refresh circuit for single-transistor memory cells

Abstract: For the cell layout in silicon-gate technology a storage capacitor is proposed that uses a field-induced nonequilibrium inversion layer as an electrode. As a sensitive refresh amplifier a gated flip-flop that can be used for one digit line at each of its two input nodes is presented. Different cells and refresh circuits have been realized in silicon-gate technologies. Cells with an area of 1600 /spl mu/m/SUP 2/(2.6 mil/SUP 2/) have been successfully operated with a READ/WRITE cycle time of 350 ns (storage capacitance 0.134 pF, digit line capacitance 0.32 pF for 64 cells per line or 128 cells per amplifier).

Admittance of p-n junctions containing traps☆

Abstract: A p-n junction containing large densities of deep levels is analyzed using a truncated space-charge approximation. The continuity equation for the occupation of deep levels is solved simultaneously with Poisson's equation to obtain the frequency dependent capacitance of a junction containing one or more levels. That portion of the capacitance which enters the field-effect transconductance is also obtained and is found to have a different frequency dependence. An apparent dependence of the deep level time constant on compensation is shown to arise from the interaction between the total charge in the levels and the electron concentration in the space-charge region. This interaction further alters all the time constants when two or more deep levels are present. The single level theory is compared with the experiments and more exact numerical calculations of Sah and co-workers, and the two level theory is compared with experimental results on neutron-irradiated junction field-effect transistors.

Battery testing method employing capacitance and dissipation factor measurements

Abstract: A method for testing electrical storage batteries employs a measurement of electrical capacitance between the battery terminal posts to indicate whether the constructional quality of the battery is acceptable and, if not, to further indicate the class of defect involved, and employs a measurement of the dissipation factor of electrical capacitance between the battery terminal posts to indicate whether the degree of oxidation of the electrode plates is within acceptable limits, which measurements and indications are preferably employed in conjunction with each other when full testing of a battery is desired but may also be used separately when only testing for a particular kind of defect is desired. The method is further characterized, in that, the measurements of capacitance and dissipation factor are made while the battery is in ''''dry'''' condition without any electrolyte present therein.

Voltage dependence of bilayer membrane capacitance

Abstract: The change in capacitance of cholesterol-hexadecyltrimethylammonium bilayer membranes upon application of relatively high dc and ac potentials was measured as a function of frequency. Capacitance increases proportional to the square of voltage were observed (0.5–1% for 100 mV dc). The amplitude of the ac component of the capacitance variation decreased with frequency until a break frequency was reached, above which the capacitance response was constant at a value about two orders of magnitude lower than the dc response. By comparison with the elastic response of the membrane and border, it was concluded the capacitance response at higher frequency was due to bilayer thickness decrease with voltage (electrostriction) while the lower frequency response was associated with a bilayer area increase. Agreement was obtained between the measured electrostriction and that calculated from membrane elasticity. Area increases with voltage calculated assuming border shrinkage as a result of an increase in contact angle were in order of magnitude agreement with the observed dc response. The effects of lenses and bowed membranes are discussed.

Capacitance of Parallel Rectangular Plates Separated by a Dielectric Sheet

Abstract: To determine the capacitance between two rectangular parallel plates separated by a dielectric sheet, the charge distribution on the plates is formulated in terms of a Fredholm integral equation of the first kind. This equation is solved numerically by a projective method using polynomial approximants. The resulting capacitance values are given in normalized graphical form, permitting capacitance determination for any practical values of dielectric constant and geometric parameters to within a few percent.

Pn junctions in polycristalline-silicon films

Abstract: Junction diodes have been fabricated in chemically deposited polycrystalline-silicon films The current-voltage characteristics indicate the predominance of recombination-generation current Minority carrier lifetimes of about 2 × 10−11 sec and 2 × 10−10 sec have been measured in 2 and 8 μm-thick films, respectively The capacitance-voltage relation has been found to be frequency dependent The capacitance decreases more rapidly with voltage at higher frequencies, consistent with the inability of trapped carriers to respond to high-frequency excitation

Dielectric Constants of Quartz

Abstract: The dielectric constants of quartz have been determined by measuring the capacitance per unit area of parallel‐plate capacitors made by depositing metallic electrodes on surfaces of thin plates of quartz cut in such a way that the major surfaces are respectively perpendicular and parallel to the optic axis. The effect of fringing of the field at the edges was eliminated by measuring the capacitance per unit area for electrodes of different sizes and extrapolating to infinite area. The dielectric constant measured with the field parallel to the optic axis is K∥=4.60. The constant in the perpendicular direction is K⊥=4.51. Both results are believed to be correct to ±0.2%.

Electronic switch actuated by proximity of the human body

Abstract: An improved contact-less electronic switch, adapted to be actuated by the approach of a human hand, with a capacitive probe insulated against the chassis and installed in the zone of approach, and connected to a capacitance detecting circuit which delivers a switching signal when the capacitance is increased by the approach of a hand, wherein the improvement comprises that the switch remains unaffected by the approach of all other substances, such as metals or insulating materials

Variable capacitance device

Abstract: This specification discloses variable capacitance devices which vary their capacitances under the influence of DC bias voltages or radiations. One embodiment comprises a PN junction diode, a dielectric thin film deposited on the surface of said junction diode at which the junction terminates and a conducting electrode deposited on the dielectric thin film, in which the area of an equivalent plate electrode formed in said junction diode is varied by changing the thickness of a depletion region. In another embodiment, a nonlinear resistance layer deposited on the dielectric thin film is employed. As a DC voltage as applied to the nonlinear resistance layer is increased, the lateral conductivity of the nonlinear resistance layer increases and the area of the equivalent plate electrode facing the conducting electrode is increased. A further embodiment employs a thin film transistor or a MIS transistor to vary the area of the equivalent plate electrode provided therein.

Photocapacitance Effects at a Cu2S–CdS Heterojunction

Abstract: The influence of trapped charge on the photovoltaic properties of an efficient Cu2S-CdS single-crystal heterojunction has been studied by a photocapacitance technique. For the nonheat-treated cell, a persistent increment in capacitance as high as 70% of the dark capacitance remained after illumination of the junction by band-gap light at 100 K. The additional capacitance is due to holes trapped in deep levels in the CdS depletion region near the interface. The trapped holes enhanced the 100 K photocurrent spectrum uniformly by a factor of 3 before heat treatment. After a 200 C heat treatment in air, the maximum trapped charge at 100 K enhanced the photocurrent by two orders of magnitude. The results are interpreted in terms of the tunneling through a conduction band spike of electrons photoexcited in the Cu2S.

High-discrimination antenna array for capacitance-responsive circuits

Abstract: A multi-element antenna array for use with capacitanceresponsive circuits to enable discrimination between human occupants and animals or packages resting on an automobile seat.

ac electrical properties and I‐V characteristics of MoO3 film under dc bias

Abstract: The ac electrical properties and the I‐V Δ characteristics of Au–MoO3–Au thin‐film sandwiches were measured under dc voltage bias. The capacitance of the samples is a strong function of the temperature and dc voltage bias. It increases as much as a factor of 20 for a 2900‐A‐thick sample as the temperature is increased; this variation is reduced with increasing voltage bias. At 325 °K the capacitance is a strong function of the dc voltage bias, decreasing from its zero‐bias value by about 50% at V = 1.5 V. The voltage dependence of the capacitance decreases with decreasing temperature, and at T = 77 °K it is essentially voltage independent. The conductance is also observed to be strongly dependent on temperature and dc voltage bias. For V≲0.6 V, it initially increases strongly with increasing temperature and reaches a maximum value at about 310 °K. With further increase in temperature, it decreases to a minimum value and then increases monotonically. For V≳0.6 V, the conductance increases monotonically wit...

Bulk and optical generation parameters measured with the pulsed MOS capacitor

Abstract: Theory and experiments are presented for the pulsed MOS capacitor when carrier generation is constant. This condition obtains when quasi-neutral bulk-region generation dominates over that in the space-charge region or when generation is due to an external excitation mechanism. It is shown how the diffusion length, surface generation velocity, and external flux can be obtained from the pulsed C-i response. This extends the usefulness of the pulsed MOS-C to narrow-gap semiconductors, such as germanium, as well as to optical generation measurements.

Nonlinear Sheath Admittance, Currents, and Charges Associated With High Peak Voltage Drive on a VLF/ELF Dipole Antenna Moving in the Ionosphere

Abstract: We consider a bare antenna consisting of two line elements driven by a VLF source and immersed in the ionosphere. Nonlinear effects associated with high voltages up to 1000 volts and with an additional induced v×B·1 voltage are included. The applied voltage is visualized as a dc effect. For various instantaneous voltage values, we obtain the distribution along the antenna of voltage and resis'ive current, sheath size, and charge per unit length. At the feed points, waveforms for the charge and both resistive and displacement currents are illustrated, assuming an applied cosine voltage form. Averaging over a cycle yields, as a function of peak bias voltage, the average power dissipated in collection of particles from the medium, the average work done in moving charge between the two half-antennas, and the average sheath conductance and capacitance. Numerical results are given for three altitudes and two antenna lengths.

Environment immune high precision capacitive gauging system

Abstract: A capacitive probe having at least two electrically conducting probe tips or electrodes centrally placed within an electrically conducting housing and axially displaced from each other within the housing. A physical dimension is measured by determining the capacitance between one probe tip and a surface, the capacitance therebetween varying with the dimension being measures. Precise machining of planar probe tips and assemblies to make them identical, their close placement, and the use of a moisture impenetrable dielectric for supporting the tips within the housing insure precision measurement and environmental independence. This precision and its maintenance is augmented by electronic excitation circuitry for the probe tips which maintain the instantaneous electric potential on each tip approximately equal and which gives an output signal whose average variation from a ground or common potential is directly indicative of the distance being gauged. Modifications to the basic probe construction include: provisions for guarding each probe tip with a substantially equal potential: thin or thick film deposition probe tip constructions; and probes having a plurality of tips for sensing a multiplicity of factors influencing the capacitance between the probe and a surface with circuits for separating the factors. A specific application of this for dielectric strip width measurement is presented.

Stored charge memory detection circuit

Abstract: A sensing circuit which is responsive to binary information represented by the level of charge in a capacitor is disclosed. The circuit comprises a differential amplifier; the nodes of which are connected to bucket brigade sense amplifier arrangements which are in turn connected to bit lines to which a plurality of memory device which store information in the form of charge are connected. Each bit line portion connected to the bucket brigade sense amplifier represents half of a bit line to which a plurality of storage devices (such as a capacitor in series with an FET gate) are connected. Each half of the bit line is also connected to a reference capacitor via an actuable FET device or other stored charge memory device. Each of the bucket brigade sense amplifiers consists of an output capacitance which is connected in parallel with the bit line capacitances of each half of the bit line via an actuable FET device. A source of voltage for charging the bit line capacitances is connected to the bit line halves via an actuable FET device and is utilized to charge the bit line capacitance, the output capacitance and a reference capacitor of one of the bit line halves. In operation, both bit line halves are charged to some voltage which is usually equal to the voltage to which the capacitance of a selected memory cell can be charged. At the same time, a reference capacitor is charged to approximately one half the voltage to which the selected cell capacitance can be charged. If the reference capacitor is to be charged to half the voltage of a storage cell, the size of the reference capacitor should be equal to that of the storage capacitor. Another way of implementing the reference capacitor is to use a reference capacitor half the size of a storage capacitor and discharge it completely each time before selecting a memory cell. If the memory cell capacitor is charged to full voltage (representing a binary ''''1'''') when the word line of the memory cell is activated for reading, no charge will flow from the bit line capacitance to the memory cell capacitance because both are at the same level. If the memory cell capacitance were empty (representing a binary ''''0'''') charge would flow from the bit line capacitance when reading occurred, filling the memory capacitor and reducing the bit line capacitor voltage by a small ion. When the bucket brigade circuit is actuated, no charge transfer occurs where the memory capacitor was full and a voltage approximately equal to the bit line charging voltage appears on one node of the differential amplifier. Where the memory capacitor was initially empty, charge transfer occurs to refill the bit line capacitance to its original level thereby depleting the output capacitance of charge and causing zero potential to be applied to one node of the differential amplifier. Simultaneously, with the appearance of the bit line charging voltage or zero at one node of the differential amplifier, a voltage equal to approximately half the bit line charging voltage appears at the other node of the differential amplifier. This results from the charging of the reference capacitance to one half the charging voltage. When reading of the reference capacitance occurs, charge from the bit line capacitance charges the reference capacitor up to its full value, depleting the bit line capacItance of an amount of charge equal to half the charge depleted from the opposite bit line capacitance when a memory cell storing a ''''0'''' is selected. When the bucket brigade sense amplifier is actuated, charge from the output capacitance thereof replenishes the bit line capacitance and leaves the output capacitance at a value of voltage approximately equal to one half of the charging voltage. In this manner, when a selected memory device associated with one half of a bit line is being read, the reference capacitance associated with the other half of the bit line is utilized to provide a voltage which is always the same regardless of the voltage on the selected device. The appropriate reference capacitor is selected by arranging the decoding such that when a memory device on one bit line half is selected, the reference capacitor on the other bit line half is always selected.

Variable capacitance semiconductor devices

Abstract: A device comprising a body of semiconductor material of one conductivity type, a film of conductive material insulatingly overlying a surface adjacent region of the body to provide a first electrode of the device, and a second electrode in contact with another region of the body is provided. A third or capacitance controlling electrode and a channel region of opposite conductivity type in the body of semiconductor material adjacent the major surface thereof between the third electrode and the surface adjacent region are also provided. In operation, a depletion producing voltage is applied between the first and second electrodes. Another voltage for controlling the capacitance of the device is applied between the second and the third electrodes to establish in the surface adjacent region a potential between the potentials of the first and second electrodes. The time constant of the capacitance of the surface adjacent region and the resistance of the channel region of opposite conductivity type is set to be short in relation to the time which would be required to establish inversion in conductivity type of the surface adjacent region in response to normal minority carrier generation therein in a structure not containing the channel region and the third electrode and to be long in relation to the frequency of operation of the device whereby the capacitance presented across the first and second electrodes is determined by the voltage applied to the third electrode.

Three application areas for SrTiO3 glass-ceramics

Abstract: The perovskite SrTiO3 can be controllably crystallized in situ in a glass matrix, and the resulting glass-ceramic displays a large peak in the dielectric constant at about 75 K (shifted from 35 K by doping and glass-chemistry techniques) and a T-1 increase in the dielectric constant below 0.1 K. This high degree of dielectric activity at cryogenic temperatures makes possible three potential applications: (1) A capacitance thermometer with a range from 0.1 to 70K which is unaffected by magnetic fields: (2) A 77 K capacitance energy-storage device; and (3) An adiabatic-depolarization cooling device below 0.1 K.Actual thermometers fabricated from this glass-ceramic (1 × 2 × 5 mm) had sensitivities ⋍ 250pF/K at 4.2 K and a linear C-T range from 1.1 to 5.2 K. It is demonstrated that this thermometer is unaffected by an intense magnetic field of 140 kG between 1.5 and 4.2 K.The field dependence of the dielectric constant at 77 K. was measured up to 180kV/cm, and these data were used to evaluate the Helmholtz en...

A Method for Computing Edge Capacitance of Finite and Semi-Infinite Microstrip Lines (Short Papers)

Abstract: This short paper describes a method for computing the edge capacitance of finite or semi-infinite sections of microstrip transmission lines. The approach is based on Galerkin's method applied in the Fourier-transform domain. It is mathematically simple and requires the inversion of rather small-size matrices.

A Network Analogue Method for Computing the TEM Characteristics of Planar Transmission Lines

Abstract: A network analogue method for calculation of the capacitance matrix of certain two-dimensional multiconductor systems is presented. The system is contained in a finite or infinite conducting rectangular boundary. An arbitrary number of parallel dielectric layers can be present, and the conductors consist of an arbitrary number of conducting strips at one or more of the dielectric interfaces. The strips are assumed to have zero thickness.

Response times of light-emitting diodes

Abstract: Response times of light emission from a GaAs 0.6 P 0.4 electroluminescent diode have been measured for stepwise applications of voltage. Turn-on times decrease either with an increase of the steady-state level of current or with superposition of a dc bias voltage. The main features of the experiment are in reasonable agreement with those of the calculated curves based on an equivalent circuit with a depletion-layer capacitance and a voltage-dependent diode conductance.

Determination of the spatial distribution of deep centers from capacitance measurements of pn junctions

Abstract: Effects of a spatial distribution of deep centers on the junction capacitance are reported for the first time. It is shown that the spatial distribution of deep centers can be calculated from capacitance data measured by both the capacitance‐voltage method and the Copeland method, if their energy level is known or assumed. The theory is examined with the experiment on silicon p+n junctions irradiated with 300‐kV protons. The analysis yields a value 0.40 eV below conduction band for the energy level of radiation‐induced defects, as well as a distribution of the defects with depth.