Showing papers on "Capacitance published in 1992"

Scaling the Si MOSFET: from bulk to SOI to bulk

Abstract: Scaling the Si MOSFET is reconsidered. Requirements on subthreshold leakage control force conventional scaling to use high doping as the device dimension penetrates into the deep-submicrometer regime, leading to an undesirably large junction capacitance and degraded mobility. By studying the scaling of fully depleted SOI devices, the important concept of controlling horizontal leakage through vertical structures is highlighted. Several structural variations of conventional SOI structures are discussed in terms of a natural length scale to guide the design. The concept of vertical doping engineering can also be realized in bulk Si to obtain good subthreshold characteristics without large junction capacitance or heavy channel doping. >

S-parameter-based IC interconnect transmission line characterization

Abstract: A methodology for extracting high-frequency IC interconnect transmission parameters directly from S-parameter measurements has been demonstrated using on-chip test structures. The methodology consists of: (1) building on-chip interconnect structures for microwave test, (2) characterizing and subtracting measurement system parasitics, (3) extracting the transmission line impedance and propagation constant (attenuation constant and phase constant) from the calibrated data, and (4) extracting the Telegrapher's Equation transmission parameters (R, L, C, and G). Additional on-chip calibration permits subtraction of pad parasitic effects. This methodology is demonstrated over a 45-MHz to 20-GHz frequency range using an example 1-cm-long, 4- mu m-wide IC interconnect built in an advanced BiCMOS technology. Variations in interconnect impedance and capacitance indicate two signal propagation modes. Significant substrate-based loss is measured at microwave frequencies. >

Electrical capacitance tomography for flow imaging: system model for development of image reconstruction algorithms and design of primary sensors

Abstract: A software tool that facilitates the development of image reconstruction algorithms, and the design of optimal capacitance sensors for a capacitance-based 12-electrode tomographic flow imaging system are described. The core of this software tool is the finite element (FE) model of the sensor, which is implemented in OCCAM-2 language and run on the Inmos T800 transputers. Using the system model, the in-depth study of the capacitance sensing fields and the generation of flow model data are made possible, which assists, in a systematic approach, the design of an improved image-reconstruction algorithm. This algorithm is implemented on a network of trans- puters to achieve a real-time performance. It is found that the selection of the geometric param- eters of a 12-electrode sensor has significant effects on the sensitivity distributions of the capacitance fields and on the linearity of the capacitance data. As a consequence, the fidelity of the reconstructed images are affected. Optimal sensor designs can, therefore, be provided, by accommodating these effects.

Single-electron capacitance spectroscopy of discrete quantum levels.

Abstract: We observe the capacitance signal resulting from single electrons tunneling into discrete quantum levels. The electrons tunnel between a metallic layer and confined states of a single disk in a microscopic capacitor fabricated in GaAs. Charge transfer occurs only for bias voltages at which a quantum level resonates with the Fermi energy of the metallic layer. This creates a sequence of distinct capacitance peaks whose bias positions directly reflect the electronic spectrum of the confined structure. From the magnetic field evolution of the spectrum, we deduce the nature of the bound states.

Multilevel metal capacitance models for CAD design synthesis systems

Abstract: An empirical model for multilevel interconnect capacitance is presented. This is the first model that allows designers to compute capacitances of arbitrary complex metal geometries. Such flexibility is achieved by a novel strategy of constructing complex geometries from simple primitive cells. Agreement with accurate simulations and measurements is within 8% over an extensive range of dimensions. >

Fast capacitance extraction of general three-dimensional structures

Abstract: K. Nabors and J. White (1991) presented a boundary-element-based algorithm for computing the capacitance of three-dimensional m-conductor structures whose computational complexity grows nearly as mn, where n is the number of elements used to discretize the conductor surfaces. In that algorithm, a generalized conjugate residual iterative technique is used to solve the n*n linear system arising from the discretization, and a multipole algorithm is used to compute the iterates. Several improvements to that algorithm are described which make the approach applicable and computationally efficient for almost any geometry of conductors in a homogeneous dielectric. Results using these techniques in a program which computes the capacitance of general 3D structures are presented to demonstrate that the new algorithm is nearly as accurate as the more standard direct factorization approach, and is more than two orders of magnitude faster for large examples. >

Design of sensor electronics for electrical capacitance tomography

Abstract: The design of the sensor electronics for a tomographic imaging system based on electrical capacitance sensors is described. The performance of the sensor electronics is crucial to the per- formance of the imaging system. The problems associated with such a measurement process are discussed and solutions to these are described. Test results show that the present design has a resolution of 0.3 femtofarad (For a 12-electrode system imaging an oil/gas flow, this represents a 2% gas void fraction change at the centre of the pipe) with a low noise level of 0.08 fF (rms value), a large dynamic range of 76 dB and a data acqui- sition speed of 6600 measurements per second. This enables sensors with up to 12 electrodes to be used in a system with a maximum imaging rate of 100 frames per second, and thus provides an improved image resolution over the earlier 8- electrode system and an adequate electrode area to give sufficient measurement sensitivity.

Multipole-accelerated capacitance extraction algorithms for 3-D structures with multiple dielectrics

Abstract: The authors describe how to extend the multiple-accelerated boundary-element method for 3-D capacitance computation to the case where conductors are embedded in an arbitrary piecewise-constant dielectric medium. Results are presented to demonstrate that the method is accurate, has nearly linear computational growth, and can be nearly two orders of magnitude faster than the standard boundary-element method based on matrix factorization. >

Method of forming a stacked capacitor with striated electrode

Abstract: A method of forming a capacitor on a semiconductor wafer includes: a) in a dry etching reactor, selectively anisotropically dry etching a capacitor contact opening having a minimum selected open dimension into an insulating dielectric layer utilizing selected gas flow rates of a reactive gas component and an inert gas bombarding component, the flow rate of the bombarding component significantly exceeding the flow rate of the reactive component to effectively produce a capacitor contact opening having grooved striated sidewalls and thereby defining female capacitor contact opening striations; b) providing a layer of an electrically conductive storage node material within the striated capacitor contact opening; c) removing at least a portion of the conductive material layer to define an isolated capacitor storage node within the insulating dielectric having striated sidewalls; d) etching the insulating dielectric layer selectively relative to the conductive material sufficiently to expose at least a portion of the external male striated conductive material sidewalls; and e) providing conformal layers of capacitor dielectric and capacitor cell material atop the etched conductive material and over its exposed striated sidewalls. The invention also includes a stacked capacitor construction having an electrically conductive storage node with upwardly rising external sidewalls. Such sidewalls have longitudinally extending striations to maximize surface area and corresponding capacitance in a resulting construction.

Real-time monitoring of immunochemical interactions with a tantalum capacitance flow-through cell

Abstract: A flow-through cell for the real-time capacitance monitoring of immunochemical interactions has been developped. It consists of a tantalum strip onto which tantalum oxide was grown electrochemically to a layer thickness as small as 5 nm. Antibody or antigen was immobilized onto the tantalum oxide surface, and binding of the corresponding analyte resulted in modification of the electrical capacitance of the system. With mouse IgG as the ligand, real-time monitoring of anti-mouse-IgG inthe nanogram per milliliter range was possible

Voltage variable capacitor.

Abstract: A voltage variable capacitor (10) has as the base substrate a silicon wafer with a layer of high resistivity semiconductor material on top of the substrate. An insulating layer (16) of a metal oxide having a dielectric constant greater than the dielectric constant of the semiconductors (12), such as zirconium titanate, is formed on top of the high resistivity layer, and a metal electrode (18) is formed on the insulating layer (16). When the electrode is energized, a depletion layer (20) is formed in the high resistivity layer. By varying the voltage applied to the electrode, the capacitance of the device is altered.

Battery state of charge monitor

Abstract: An apparatus and method for monitoring the state of charge of the battery having a shunt resistor connected in series with a battery and an integrating circuit connected across the terminals of the shunt resistor which includes a large capacitance element having the capability to store charge for long periods of time, so that the integration can be performed along the same curve even if power to the integrating circuit is interrupted during continuous or intermittent use. The apparatus and method are applicable to batteries for automotive vehicles. Temperature compensation schemes to adjust the state of charge monitoring circuit to correct for changes in battery performance characteristics with temperature are provided. A circuit for detecting the existence of a defective battery cell is provided. A system for monitoring charging and discharging of the battery over time and identifying various battery conditions and potential battery or battery charging system failures is provided.

A new cylindrical capacitor using hemispherical grained Si (HSG-Si) for 256Mb DRAMs

Abstract: This HSG-Si cylindrical capacitor structure achieves a cell capacitance of 30 fF with 04 mu m-high storage electrode in a 072 mu m/sup 2/ cell area A new selective etching technique using a low-pressure vapor hydrogen fluoride is developed to form the cylindrical capacitor electrode The high selective etching (2000 times) of borophosphosilicate-glass to SiO/sub 2/ is realized Disilane molecule irradiation in ultra-high vacuum chamber achieves the HSG-Si formation on the whole surface of phosphorous doped amorphous Si cylindrical electrode >

Binary encoded multiple frequency rf identification tag

Abstract: A tag (10) for identifying an item to which it is attached includes an inductance (L) connected in parallel with a capacitance. The capacitance includes a plurality of individual capacitors (C1, C2, C3, C4, C5), each of a predetermined different capacitance. The individual capacitors (C1, C2, C3, C4, C5) are connected to the inductance (L) to establish a resonant circuit (20) having a predetermined resonant frequency. At least one of the capacitors (C1, C2, C4) includes a dimple (12) for shorting the capacitor when the tag (10) is exposed to electromagnetic energy at the predetermined resonant frequency. The shorted capacitor establishes a second resonant frequency which may be used to identify which capacitor (C1, C2, C4) has become shorted. A binary '1' is assigned to either the shorted capacitor (C1, C2, C4) or the non shorted capacitor (C3, C5) and a binary '0' is assigned to the capacitors which are not assigned a binary '1', the binary '1's and '0's combining to establish a numeric code uniquely associated with the tag (10).

Device application and structure observation for hemispherical‐grained Si

Abstract: A polycrystalline‐silicon surface with hemispherical grains (HSG) is deposited by low‐pressure chemical vapor deposition at 590 °C. At the temperature, 590 °C, the structure of the Si film just after deposition is amorphous, but crystallization of the amorphous Si occurs to produce HSG‐Si during annealing after deposition. The HSG‐Si is formed by the nuclei generation on the clean amorphous‐Si surface and by the crystalline growth during annealing. The surface area of the HSG‐Si film is about twice as large as Si films deposited at other temperatures. By applying the HSG‐Si film as the storage electrode for a 64‐M‐bit dynamic random access memories (DRAM) stacked‐capacitor with a SiO2/Si3N4 dielectric film, a capacitance of twice the value is obtained. The increase of the capacitance makes it possible to reduce the DRAM cell area, even by using a relatively thick dielectric film for higher reliability.

High area capacitor formation using material dependent etching

Abstract: The invention provides a capacitor having increased capacitance comprising one or more main vertical trenches (16) and one or more lateral trenches (18) extending off the main vertical trench. The capacitor has alternating first and second regions (12, 14), preferably silicon and non-silicon regions (for example, alternating silicon and germanium or alternating silicon and carbon regions). The etch characteristics of the alternating regions are utilized to selectively etch lateral trenches thereby increasing the surface area and capacitance of the capacitor. A method of fabricating the capacitors is also provided.

Battery operated capacitance measurement circuit

Abstract: A capacitance measuring circuit uses only a DC voltage source to perform the capacitance measurement. For this purpose, the circuit is arranged to charge an unknown capacitor which is being measured from a DC source and to discharge the capacitor through a constant current circuit such that the discharge voltage across the capacitor decreases linearly from its initial value to a predetermined, final value. The measurement circuit monitors the time taken by the capacitor to discharge in order to determine the capacitance value.

Capacitor used in an integrated circuit and comprising opposing electrodes having barrier metal films in contact with a dielectric film

Abstract: On a first conductor layer of a capacitor element of an IC and in contact with a dielectric film made of a particular dielectric material, a first barrier metal film is made of platinum, palladium, tantalum, or titanium nitride. A second barrier metal film is made of a similar material in contact with the dielectric film and on a second conductor layer. The particular dielectric material is either tantalum oxide or a perovskite oxide, such as strontium titanate or a composite of lead zirconate and lead titanate. In cooperation with such a dielectric film, the first and the second barrier metal films make it possible to provide a compact capacitor having a great and reliable capacitance. The capacitor element is manufactured like a conventional one except for use of the particular dielectric material and for manufacturing steps of forming the first and the second barrier metal films and may be an MOS, MIS, or MIM capacitor or a multilayer wired capacitor.

Unified MOSFET model

Abstract: We present a basic analytical MOSFET model which describes both the below and above threshold regimes of device operation. The description is based on a charge control model which uses one unified expression for the effective differential channel capacitance. The model also accounts for series drain and source resistances, velocity saturation in the channel, finite output conductance in the saturation regime, and for the threshold voltage shift due to drain bias induced lowering of the injection barrier between the source and the channel (DIBL). The model parameters, such as the effective channel mobility, the saturation velocity, the source and drain resistances, etc. are extractable from experimental data. The model has been incorporated into our simulator, AIM-Spice. We apply the characterization procedure based on this model to a MOSFET with a quarter micron gate length and obtain excellent agreement with experimental data.

Reactive power compensator.

Abstract: A system and method for determining and providing reactive power compensation for an inductive load. A reactive power compensator (50, 50') monitors the voltage and current flowing through each of three distribution lines (52a, 52b, 52c), which are supplying three-phase power to one or more inductive loads. Using signals indicative of the current on each of these lines when the voltage waveform on the line crosses zero, the reactive power compensator determines a reactive power compensation capacitance that must be connected to the lines to maintain a desired VAR level, power factor, or line voltage. Alternatively, an operator can manually select a specific capacitance for connection to each line, or the capacitance can be selected based on a time schedule. The reactive power compensator produces control signals, which are coupled through optical fibers (102/106) to a switch driver (110, 110') to select specific compensation capacitors (112) for connections to each line. The switch driver develops triggering signals that are supplied to a plurality of series-connected solid state switches (350), which control charge current in one direction in respect to ground for each compensation capacitor.

Midgap states in a‐Si:H and a‐SiGe:H p‐i‐n solar cells and Schottky junctions by capacitance techniques

Abstract: The midgap density of states (MGDOS) in a‐SiGe:H alloys is investigated by capacitance measurements on p‐i‐n solar cells. Past work on thick a‐Si:H Schottky barriers is extended to thin a‐SiGe:H p‐i‐n cells. Four methods of determining the MGDOS from the measured capacitance are described, and each is applied to two p‐i‐n devices having 0% and 62% Ge in the i layers, respectively. The first method involves fitting an equivalent circuit model to the measured admittance. Close agreement is found over a wide range of temperature and frequency. The single junction model is shown to apply equally well to p‐i‐n and Schottky diodes, justifying the neglect of the n‐i junction and thin doped layers in the p‐i‐n admittance analysis. A second method determines g0 from the limiting capacitance at high temperature. The third and fourth methods extract g0 from the dependence of capacitance on voltage bias. One of these is novel, presented here for the first time. Thus, a unique feature of this study is the application ...

Effectiveness of multiple decoupling capacitors

Abstract: The effectiveness of using the parallel combination of large-value and small-value capacitors to increase the frequency coverage of either one and overcome the effect of lead inductance is examined. Computed and experimental results are given that show this scheme is not significantly effective. The improvement at high frequencies is at most 6 dB over the use of only the large-value capacitance. >

Determination of the density of Si-metal interface states and excess capacitance caused by them

Abstract: Schottky diodes were fabricated by evaporation of Al on a strongly etched n-type Si surface for 3 min after mechanical cleaning. The measurements of one of the better working of the Al-nSi diodes has been carried out at room temperature. Two expressions were found for the ideality factor n by supposing that all the interface states at first are in equilibrium with the metal and then with the semiconductor. The diode showed non-ideal I–V behaviour with an ideality factor of 1.46. The density distribution of interface states was obtained from the forward bias I–V characteristics. Non-linearity or curvature in the reverse bias C -2 − V plots was a quantity called the “excess capacitance” C 0 caused by the presence of the interface states. The excess capacitance was observed to decrease with increasing frequency: this behaviour was ascribed to the fact that the apparent density of the interface states decreases with increasing frequency. In addition, the parameters obtained from C − V characteristics were corrected by means of a simple graphical method for excess capacitance suggested by Vasudev et al. and of a theoretical model of an MIS structure introduced by Fonash.

Selective detection of organic molecules with polymers and supramolecular compounds: application of capacitance, quartz microbalance and calorimetric transducers

Abstract: Different ‘prototype’ organic coatings were used for three different transducers with the aim of optimizing the selective detection of organic molecules. The different thermodynamically and kinetically controlled sensor parameters were obtained from capacitance, quartz microbalance and calorimetric transducers. The results are discussed in the framework of different interaction mechanisms which occur in the detection of one organic gas component with its specific molecular weight, dielectric constant or heat of interaction.

Method for manufacturing a capacitor of a semiconductor device

Abstract: Disclosed is a method for manufacturing a capacitor of a semiconductor device After forming a polycrystalline layer (50) composed of grains with microscopic structure to include an impurity (70) in them, the polycrystalline layer is etched to cut the boundary portions of the grains, thereby allowing the surface of the polycrystalline layer to be rugged The micro-trenches (1) or micro-pillars (11) are formed by using the oxide layer or an anisotropic etching after exposing the surface of the first rugged polycrystalline layer, and epitaxial grains (95) are formed by epitaxial growth, so that cell capacitance can be further increased The simple process allows the formation of a reliable semiconductor device having regularity and reproducibility, and capable of increasing and adjusting the cell capacitance easily

Theory of junction between two-dimensional electron gas and p-type semiconductor

Abstract: The authors develop a theory of the junction between a two-dimensional electron gas and a three-dimensional p-type semiconductor contact. The cut-in voltage of such a junction depends on the density of the 2-D electron gas. Hence, at low currents, the device current varies exponentially with the 2-D gas density. The unique features of such junctions include a very small effective cross section (equal to the product of the thickness of the 2-D gas and the device width) and, hence, a small junction capacitance and a small device current at large current densities. Using a conformal mapping technique, the authors calculate potential and field distributions and find the differential device capacitance as a function of bias. They then calculate the output device characteristics for different gate voltages. The results of a 2-D self-consistent Monte Carlo simulation for such a structure are presented. This simulation clearly shows that electrons and holes are localized in the vicinity of the 2-D electron gas even at high drain biases. >

Detector for force, acceleration or magnetism with respect to components in multi-dimensional directions

Abstract: On the upper surface of a flexible substrate, four displacement electrodes are arranged. A fixed substrate is arranged thereabove, and fixed electrodes opposite to the displacement elctrodes are respectively arranged on the fixed substrate. These displacement electrodes and the fixed electrodes form capacitance elements C1 to C4, respectively. A columnar working body is fixed on the lower surface of the flexible substrate. A bending is produced in the flexible substrate on the basis of an acceleration exerted thereon. As a result, capacitance values of the respective capacitance elements C1 to C4 vary. The capacitance values of the capacitance elements C1 to C4 are converted to respective voltage values V1 to V4. A component in the X-axis direction is obtained as Vx=(V1+V4)-(V2+V3), a component in the Y-axis direction is obtained as Vy=(V1+V2)-(V3+V4), and a component in the Z-axis direction is obtained as Vz=V1+V2+V3+V4.

Micromachined atomic force I microprobe with integrated I I capacitive read-out I

Abstract: . We developed a micromachining process for the fabrication of highly sensitive capacitor probes to be used for displacement measurement of an atomic force cantilever. The capacitive structure consists of two adjacent single-crystal silicon beams, one carrying a sharp tip for the force interaction, the other being the counter-electrode. The air gap of 1.5 pm separating the two electrodes is obtained by removal of the oxide in between by selective etching. The capacitance has a typical value of -0.2 pF. Forces acting on the tip induce a bending of the cantilever and change the caDacitance which can be detected bv electronic circuits. 1. Introduction Using capacitive variation to sense physical displace- ments represents an interesting alternative to optical, tunneling or piezoresistive methods. Sensors that use single-crystal silicon as highly elastic material and capacitance change as the readout principle are known to be reliable and accurate [I]. Additionally, thermal silicon dioxide provides good electrical insulation and allows, in combination with highly doped silicon, the

Ground-state energies of one- and two-electron silicon dots in an amorphous silicon dioxide matrix.

Abstract: The one- and two-electron ground-state energies of a silicon sphere embedded in an amorphous silicon dioxide matrix are calculated as a function of the sphere size. The electron-electron interaction and polarization effects are treated by perturbation; our quantum-mechanical calculation is valid for small spheres with radii between 10 and 40 \AA{}. For large spheres, classical electrostatics is used. A universal effective capacitance is defined in terms of the difference in the ground-state energies of the (n+1)- and n-electron cases, which agrees with the usual concept of capacitance in the classical limit.