Showing papers on "Capacitance published in 1994"

Paintbrush stylus for capacitive touch sensor pad

Abstract: A proximity sensor system includes a touch-sensor pad with a sensor matrix array having a characteristic capacitance on horizontal and vertical conductors connected to sensor pads. The capacitance changes as a function of the proximity of an object or objects to the sensor matrix. The change in capacitance of each node in both the X and Y directions of the matrix due to the approach of an object is converted to a set of voltages in the X and Y directions. These voltages are processed by circuitry to develop electrical signals representative of the centroid of the profile of the object, i.e, its position in the X and Y dimensions. Noise reduction and background level setting techniques inherently available in the architecture are employed. A conductive paintbrush-type stylus is used to produce paint-like strokes on a display associated with the touch-sensor pad.

Modeling the "Effective capacitance" for the RC interconnect of CMOS gates

Abstract: With finer line widths and faster switching speeds, the resistance of on-chip metal interconnect is having a dominant impact on the timing behavior of logic gates. Specifically, the gates are switching faster and the interconnect delays are getting longer due to scaling. This results in a trend in which the RC interconnect delay is beginning to comprise a larger portion of the overall logic stage delay. This shift in relative delay dominance from the gate to the RC interconnect is increased by resistance shielding. That is, as the gate "resistance" gets smaller and the metal resistance gets larger, the gate no longer "sees" the total net capacitance and the gate delay may be significantly less than expected. This trend complicates the timing analysis of digital circuits, which relies upon simple, empirical gate delay equations for efficiency. In this paper, we develop an analytical expression for the "effective load capacitance" of a pc interconnect. In addition, when there is significant shielding, the response waveforms at the gate output may have a large exponential tail. We show that this waveform tail can strongly influence the delay of the RC interconnect. Therefore, we propose an extension of the effective capacitance equation that captures the complete waveform response accurately, with a two-piece gate-output-waveform approximation. >

Ferroelectric properties and fatigue of PbZr0.51Ti0.49O3 thin films of varying thickness: Blocking layer model

Abstract: Ferroelectric capacitors having Pt bottom and top electrodes and a ferroelectric film of composition PbZr0.51Ti0.49O3 (PZT) were fabricated and investigated. The PZT films of thicknesses varying from 0.12 to 0.69 μm were prepared by organometallic chemical‐vapor deposition. Annealed capacitors were investigated by capacitance, hysteresis, and pulse switching measurements. It is found that the thickness dependence of the reciprocal capacitance, the coercive voltage, and the polarization measured by pulse switching can all be explained by a blocking layer model, in which a dielectric layer of thickness dbl and relative permittivity ebl is situated between the PZT film and an electrode. It is shown that (i) the coercive field is independent of thickness having a value of 2.4 V/μm; (ii) the ratio ebl/dbl is in the range 20–28 nm−1; (iii) the voltage across the blocking layer is proportional to the polarization, Vbl=cP, where c=4.1±0.5 V m2/C; and (iv) the polarization depends on the electric field in the PZT layer, independent of thickness. Pulse switching endurance measurements showed that in the saturation range the fatigue for these ferroelectric capacitors is determined by the pulse voltage and is independent of the thickness.

Object position and proximity detector

Abstract: A proximity sensor system includes a sensor matrix array having a characteristic capacitance on horizontal and vertical conductors connected to sensor pads. The capacitance changes as a function of the proximity of an object or objects to the sensor matrix. The change in capacitance of each node in both the X and Y directions of the matrix due to the approach of an object is converted to a set of voltages in the X and Y directions. These voltages are processed by analog circuitry to develop electrical signals representative of the centroid of the profile of the object, i.e, its position in the X and Y dimensions. The profile of position may also be integrated to provide Z-axis (pressure) information.

Capacitance-based proximity with interference rejection apparatus and methods

Abstract: Apparatus and method for a capacitance-based proximity sensor with interference rejection. A pair of electrode arrays establish a capacitance on a touch detection pad, the capacitance varying with movement of a conductive object near the pad. The capacitance variations are measured synchronously with a reference frequency signal to thus provide a measure of the position of the object. Electrical interference is rejected by producing a reference frequency signal which is not coherent with the interference.

Apparatus for measuring voltages and currents using non-contacting sensors

Abstract: An apparatus for performing non-contacting measurements of the voltage, current and power levels of conductive elements such as wires, cables and the like includes an arrangement of capacitive sensors for generating a first current in response to variation in voltage of a conductive element. Each sensor is positioned in an electric field of the conductive element, and is thereby coupled to the conductive element through a coupling capacitance. A reference source drives the capacitive sensor arrangement at a reference frequency so as to induce the flow of a reference current therethrough. A measurement network is disposed to calculate the coupling capacitance based on a measurement of the reference current, and to then determine the voltage in the conductive element based on the first current and the coupling capacitance. Measurements of a composite current through single or multiple-element conductors may be effected using a similar procedure, wherein the composite current induces a measurement current to flow within a set of coils positioned in a predetermined manner proximate the conductor. In both current and voltage measurements a balancing procedure may be employed, in which a measurement signal is balanced by a feedback signal so as to improve accuracy and reduce the effects of stray coupling.

Semiconductor device and manufacture thereof

Abstract: PROBLEM TO BE SOLVED: To enlarge the surface area of a capacitor storage electrode to increase capacitance of a fine-structured and integrated semiconductor device for memory SOLUTION: As a preparative layer of a capacitor storage electrode 25 formed on a semiconductor device, two or more layers of films each containing impurity in different density or different material are formed An aperture is provided by selectively removing a predetermined area of the preparative layer and etching is performed Due to the different etch rates in the preparative layer, the sidewall surface of the aperture is bellows-shaped After a conductive film is deposited on the sidewall surface of the aperture to form the capacitor storage electrode 25, the preparative layer is removed Furthermore, a capacitor dielectric film 26 and a capacitor counter electrode 27 are formed on the capacitor storage electrode 25 Consequently, the surface of the cylindrical capacitor storage electrode 25 is bellow-shaped without high-temperature heat treatment so that the surface area is enlarged to increase capacitance

Vertical insulated gate transistor and method of manufacture

Abstract: A vertical insulated gate transistor such as a UMOSFET is manufactured. A source region of first conductivity type is formed on the bottom surface of a substrate. A base region of second conductivity type is formed on the source region. A low-impurity-concentration drift region is formed on the base region. On the top surface of this multilayer structure, a truncated U groove is formed. A buried gate electrode is formed inside the truncated U groove. This structure is effective to reduce gate-drain capacitance Cgd, gate-source capacitance Cgs, and drain resistance r d , thereby realizing a high-frequency high-output device. A distance between the gate and the drain is determined in a self-aligning manner, so that a fine structure and a high-frequency operation are easily realized and production yield is improved.

An experimental high-density DRAM cell with a built-in gain stage

Abstract: A new high-density DRAM cell concept is proposed and experimentally demonstrated. This cell, composed of two transistors and one capacitor, generates a large bit line signal with a small cell capacitance during the read cycle. Since it does not need a large storage capacitance and one transistor is stacked on the top of the other transistor, the cell size is small and can be easily scaled down for future generations of memory devices. The unit cell size fabricated using a 4 M SRAM process without any process modification is 1.8 /spl mu/m/spl times/2.85 /spl mu/m. The proposed cell can be adopted to store multi-bit information. The fabricated prototype cell shows a resolution of about 3.5 bit. >

Multilayer piezoelectric ceramics for two-dimensional array transducers

Abstract: In medical ultrasound imaging, 2-D array transducers have become essential to implement dynamic focusing and phase-correction in the elevation dimension as well as real-time volumetric scanning. Unfortunately, the small size of a 2-D array element results in a small clamped capacitance and a large electrical impedance near resonance. These elements have poor sensitivity because their impedance is much higher than the electrical impedance of the transmit and receive circuitry. Sensitivity can be improved by using an N layer structure of PZT ceramic with the layers connected acoustically in series and electrically in parallel. For the multilayer ceramic (MLC), the damped capacitance is multiplied by a factor of N/sup 2/ and the electrical impedance by 1/N/sup 2/ compared to a single layer element of the same dimensions. A 3/spl times/43 phased-array transducer has been fabricated using 3 layer PZT-5H material. Each element had a thickness of 0.66 mm and an area of 0.37/spl times/3.5 mm. The MLC was manufactured using thick film technology with plated-through vias to electrically interconnect the electrode layers. The completed transducer was compared to a single layer control array of similar dimensions. With a light epoxy backing and a /spl lambda//4 matching layer, the MLC array elements had an impedance of 100 /spl Omega/ at series resonance of 2.25 MHz, compared to 800 /spl Omega/ for the control elements. The lower impedance of the MLC elements resulted in a minimum round-trip insertion loss of 24.0 dB, compared to an 34.1 dB for the control array elements. These results were consistent with KLM modeling. B-scan images were made of cysts in a tissue-mimicking phantom and of the left kidney in vivo. The images clearly showed a higher signal-to-noise ratio for the MLC array compared to the control. As a result, 2-D arrays made of multilayer ceramics can be used to form images at a higher frequency and greater range than single layer arrays. >

The use of parasitic nonlinear capacitors in class E amplifiers

Abstract: The most common class E amplifier configuration uses a single transistor with a shunt capacitor and a series resonant output filter. Until now a linear shunt capacitance has been assumed. However, to achieve operation at 900 MHz and above, it is of interest to rely solely upon the nonlinear parasitic collector-substrate capacitance of the transistor. An analytical theory for operation at 50% duty cycle and nonlinear capacitance is presented in this correspondence, and the effects on the power capability of the amplifier are discussed. >

An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology

Abstract: For future ULSI DRAMs beyond the 256 Mb generation, several circuit techniques and memory cell structures have been proposed to meet the requirement of high performance at low voltage. These solutions frequently involve complicated processing steps and/or the ultimate limitations of current Si-MOS devices. DRAM on silicon on insulator (SOI) substrate is a more simple solution to the problem. Thin-film SOI structures with isolation by implanted oxygen (SIMOX) process are under investigation for SRAM and logic. A SOI-DRAM test device with 100 nm thick SOI film has been fabricated in 0.5 /spl mu/m CMOS/SIMOX technology. With this 64 kb SOI-DRAM the bit-line to memory cell capacitance ratio Cb/Cs is reduced by 25% compared with the reference bulk-Si DRAM, because of the decreased junction capacitance. RAS access time tRAC is 70 ns at 2.7 VVcc, as fast as the equivalent bulk-Si device at 4 VVcc. The clock timing in this DRAM is not optimized, so access time should improve with well-tuned clocks. The boosted-level generator with body-contact structure enhances the upper Vcc margin and the reduced body-effect of sense-amplifier transistors improves the lower Vcc margin. The SOI-DRAM has an operating Vcc range from 2.3 V to 4.0 V. >

Method of and apparatus for providing offset for light detector

Abstract: The invention provides a solid state light imager or x-ray detector including an array of rows and columns of elements, each element including a photo diode, which converts photons to an electrical signal, and a transistor. Each photo diode has a capacitance associated with it. The cathode of the photo diode in each element is connected to the source of the transistor in the element. The amount of charge removed from each photo diode, after exposure to light, is used to create an image. The image is capable of accurate measurement of charge removed from the photo diodes after the array has been exposed to light, using unipolar measuring circuitry, in spite of charge retention by the transistors and a problem caused by the combination of changes in row voltage and parasitic row to column capacitance.

Radio frequency identification tag and method

Abstract: A method of and apparatus for identifying an item to or with which a radio frequency identification tag is attached or associated is provided. The tag is made of a nonconductive material to have a flat surface on which a plurality of circuits are pressed, stamped, etched or otherwise positioned. Each circuit has a capacitance and an inductance. The capacitance is formed from the capacitive value of a single capacitor. The inductance is formed from the inductive value of a single inductor coil having two conductive ends each connected to the capacitor. Each tag is associated with a binary number established from a pattern of binary ones and zeros which depend on the resonance or nonresonance of each circuit, respectively and the circuits position with respect to the binary table. The binary number may be converted to a decimal number using the binary table for conversion.

Semiconductor element and semiconductor memory device using the same

Abstract: A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.

Adiabatic Computing with the 2n-2n2d Logic Family

Abstract: Low-energy computing is an idea whose time has come. Applications include the smallest systems (where battery size and weight are crucial) as well as the largest systems (where power supply and cooling are crucial). To turn an F E T on or off requires transferring a certain amount of energy (the switching energy). The energy dissipated during this transfer need not be related to the energy transferred, but in ordinary CMOS logic circuits both quantities are on the order of $CV,2,, where C is the capacitance of a typical node, and V d d is the operating voltage. This level of dissipation is unavoidable if a l l the needed electrons are extracted from the V d d terminal of the power supply and ret,urned to the ground terminal. The essential idea of adiabatic computing is to construct circuits that allow each needed electron to be extracted at the lowest feasible voltage and returned at the highest feasible voltage. Ramp-like power/clock signals are required. Obviously it is advantageous to reduce c and V d d , but there are limits; in any case for the purposes of this paper we take such reductions for granted and show how dissipation can be further reduced at any particular V d d and c. The theoretical limit on dissipation is 0 for logically reversible operations, and kT for logically irreversible operations (1). Since kT is six or seven orders of magnitude below present-day values of $CV2d, there is considerable room for compromise. The logic family considered here, which we call 2N-2N2D, emphasizes overall system feasibility and throughput, while providing energy savings of “only” half an order of magnitude or so. Unlike previous diode-based energy recovery schemes (2; 3; 4) our major design goal was to present a nearly constant, data-independent capacitive load to the clock even though it makes 2N-2N2D about twice as complex as 1T1D (4). Constant load is vital, permitting operation from “stored energy” clock drivers. We have detailed simulations of such a clock driving a 6000-bit 2N-2N2D shift register ring, recovering over 75% of the transferred energy.

Modeling the influence of the transistor gain ratio and the input-to-output coupling capacitance on the CMOS inverter delay

Abstract: An improved model for the ramp response of a CMOS inverter has been derived where the influences of the short-circuit current and the input-to-output coupling capacitance are considered. These effects modify the ideal linear relationship between the inverter propagation delay and the input ramp rise/fall time by adding a term proportional to the charge supplied by the short-circuiting transistor. This term is shown to contain first- and second-order contributions of the input ramp rise/fall time where the second-order contribution effectively models the propagation delay roll-off for slow input ramps. Both the first and the second-order effects are found to be affected by the P-to-N-channel gain ratio. The model shows excellent agreement with SPICE level 3 simulations; even when the short-circuiting transistor has a driving capability twice that of the charging/discharging transistor the error in the propagation delay is only about 2% for a slow input ramp (input-to-output slope-ratio at V/sub DD//2 equal to 1:2). >

Form and capacitance of parallel-plate capacitors

Abstract: In basic electrostatics, the formula for the capacitance of parallel-plate capacitors is derived, for the case that the spacing between the electrodes is very small compared to the length or width of the plates. However, when the separation is wide, the formula for very small separation does not provide accurate results. In our previously published papers, we used the boundary element method (BEM) to derive formulas for the capacitance of strip and disk capacitors that are applicable even when the separation is large. In this paper, we present results and formulas for the capacitances of square and rectangular capacitors. >

Stray capacitances of two winding transformers: equivalent circuit, measurements, calculation and lowering

Abstract: As long as it works linearly, a two winding transformer is, from an electrostatic point of view, a three port system. Its capacitance matrix includes six independent values. Consequently, whatever its shape, introducing six capacitances in the right places of the equivalent circuit allows the user to account for the whole electrostatic behaviour of this component. With such an equivalent circuit, resonance frequencies can be computed and, reversely, the six capacitances are all deducible from measured resonance frequencies. Thus, using this circuit by hand or by software, interwinding currents of real electronic circuits can be forecasted together with parasitic resonances related to the transformer. After this global approach, a microscopic approach is adopted. A closer look at the winding layer shape and then, at the wire shape itself leads to two simple models which allow the six capacitances of the equivalent circuit to be computed by hand. Values found are approximate but, thanks to analytical expressions, two design rules leading to lower capacitance values are inferred. Measurements are presented to establish the reliability of the equivalent circuit and to evaluate the interest of the proposed designing rules. >

Method for manufacturing a semiconductor device

Abstract: A method for manufacturing a semiconductor device, wherein a thin film of tantalum oxide is formed as a dielectric film in a capacitor element, increases capacitance per unit area and reduces a leakage current in the capacitor element of DRAM memory cells. The method includes steps of forming a polysilicon film constituting a lower electrode of the capacitor element, removing a natural oxide film from the surface of the polysilicon film, nitriding the surface of the polysilicon by rapid thermal nitriding (RTN) using lamp-annealing, forming a tantalum oxide film, densifying and nitriding consecutively the tantalum oxide film, and forming an upper capacitor electrode thereon. The capacitor element formed by the method has a large capacitance per unit area Cs=13.8 fF/ mu m2.

Method of making a semiconductor device using a low dielectric constant material

Abstract: This invention provides a process for making a semiconductor device with reduced capacitance between adjacent conductors. This process can include applying a solution between conductors 24, and then gelling, surface modifying, and drying the solution to form an extremely porous dielectric layer 28. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.

Capacitance spectroscopy in quantum dots: Addition spectra and decrease of tunneling rates

Abstract: A theoretical study of single electron capacitance spectroscopy in quantum dots is presented. Exact diagonalizations and the unrestricted Hartree-Fock approximation have been used to shed light over some of the unresolved aspects. The addition spectra of up to 15 electrons is obtained and compared with the experiment. We show evidence for understanding the decrease of the single electron tunneling rates in terms of the behavior of the ! → 0 spectral weight function. Single electron capacitance spectroscopy (SECS) [1,2] has been a breakthrough in the experimental knowledge of the electronic structure of a quantum dot (QD). Ashoori and co-workers [1,2] have been able to determine the energies required to introduce electrons one by one, from 0 to 50, into a QD. The electrons tunnel into the QD by means of a vertical gate bias, and change the capacitance of the device. The measurement of that capacitance as a function of the Fermi energy EF in one electrode shows a discrete set of almost equally spaced peaks of different intensities. A peak appears whenever EF = � (N) = E0(N) − E0(N − 1), with E0(N) being the ground state (GS) energy of N electrons in the QD. In this way,

Effect of a transmission line resonator on a small capacitance tunnel junction.

Abstract: We have measured the current-voltage characteristic of a small capacitance tunnel junction coupled to a transmission line resonator. We calibrate the resonator using the sharp resonances displayed by the junction in the superconducting state, which corresponds to the pumping of the modes of the resonator by the ac Josephson current. With this calibration, we explain quantitatively the nonlinearity of the junction characteristic in the normal state as being due to the process by which a single electron tunnels by emitting a photon, the basic process of the theory of the effect of the electromagnetic environment on tunneling.

Method of decreased interlayer dielectric constant in a multilayer interconnect structure to increase device speed performance

Abstract: The RC time constant of a semiconductor device is reduced by decreasing the capacitance C. The decrease in capacitance is achieved by replacing the interlayer silicon dioxide (dielectric constant of 4.0) with air (dielectric constant of 1.0). Alternatively, the air space can also be filled with another low dielectric constant material, such as an organic material having a dielectric constant in the range of about 2.2 to 3.4. In either case, the final effective dielectric constant of the device is lowered. As a result of lowering the effective dielectric constant, a smaller RC time constant is achieved, which results in higher device speed.

A shift register useful as a select line scanner for a liquid crystal display

Abstract: A shift register for scanning a liquid crystal display includes cascaded stages. A given stage is formed with an input transistor switch that is responsive to an output pulse of a stage upstream in the chain of the cascaded stages. The input transistor switch charges a capacitance associated with a control electrode of a switched pull-up output transistor. The voltage in the capacitance conditions the output transistor for generating an output pulse when subsequently a clock signal occurs to the output transistor. A clamping transistor discharges the capacitance in a manner to prevent further generation of the output pulse when subsequent pulses of the clock signal occur. The clamping transistor is responsive to an output pulse of a stage downstream in the chain. An impedance that is developed at the control electrode is substantially higher after the clamping operation occurs and remains high for most of the vertical interval.

Apparatus and methods for measuring and detecting variations in the value of a capacitor

Abstract: A method measures the value of a capacitor and detects small variations in the value of a capacitor around a reference value. The capacitance of the capacitor may be determined by applying a voltage input having a known amplitude and wave form, V, to an RC circuit having a substantially known or constant load impedance, R, and sampling the voltage across the resistor (6 or 16) or capacitor (8 or 14) at a precisely controlled elapsed time interval, T. The method permits detector circuits to be created for measuring small variations in value with precision and accuracy. Solid state keypads (30) incorporating sensor cells (32) and software algorithms provide human interface systems which are not subject to environmentally induced errors or errors due to component aging.

Effect of CMOS driver loading conditions on simultaneous switching noise

Abstract: A model for simultaneous switching noise (SSN) for CMOS including the effect of negative feedback and loading conditions is presented. A level 1, SPICE-type device model is used with V/sub TN/=|V/sub TP/| for the simulations. An analysis of the loading conditions is conducted since no prior knowledge of this is assumed in the design of the package. The sensitivity of SSN to the load capacitance is investigated. Equations defining a critical capacitance governing SSN are included. Output buffers normally drive receivers through bond wires, signal traces, pins, and the board traces. For the short trace, the output is modeled as a lumped inductance and for the long trace, as a transmission line. Such a condition at the output will alter the current that defines the noise. Equations are presented for the critical inductance and the transmission line characteristic impedance. Above these critical values, these parameters will tend to decrease the noise generated. Finally, a practical package structure is modeled which takes into account the effects of the total loading conditions. >

Adaptive Compensation of Piezoelectric Sensoriactuators

Abstract: An adaptive filter is used to estimate the feedthrough capacitance of a piezoelectric sensoriactuator in this work. The mechanical response of the piezostructure is resolved from the electrical response of the piezoelectric device through standard adaptive signal processing tech niques. Two common adaptive algorithms are reviewed for the given application: the LMS and the RLS. For spectrally white inputs the adaptation of the digital compensator yields a filter output which is proportional to the electrical response of the piezoelectric device. Thus, the remaining elec trical signal consists of the charge due to the mechanical response of the piezostructure. The adap tive filter converges to a combination of the feedthrough capacitance and the real portion of the mechanical piezostructure response, and the filter error is the quadrature component of the mechanical response. Preliminary results from the theoretical analysis and numerical simulations indicate that, under certain conditions, adaptive signal ...

Separation and analysis of diffusion and generation components of pn junction leakage current in various silicon wafers

Abstract: An analytical method to separate the diffusion and generation components of pn junction leakage currents is developed The voltage dependence between reverse current and capacitance in pn junctions is measured, and an approximately linear relationship between current density (J) and depletion width (W) is derived In this relationship, the diffusion component corresponds to linearly extrapolated value of J at W=0, and the generation component corresponds to the rate at which J increases with W as voltage is applied This method allows both components of the leakage current to be obtained for Czochralski, epitaxial, and intrinsic gettering wafers Separated diffusion components strongly depend on silicon wafers mainly due to the change of minority carrier density and the diffusion of minority carriers On the other hand, the generation component increases with increases in the electric field applied to the junction for all wafers We found that this electric field effect on the generation component can be