Topic
Capacitive coupling
About: Capacitive coupling is a research topic. Over the lifetime, 5547 publications have been published within this topic receiving 57712 citations.
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Patent•
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TL;DR: In this article, an AC coupling capacitor at the signal terminal has a timing circuit in sync to the voltage wave and relative to impedance of the return electrodes, and a voltage comparator after the voltage detection forms a square wave.
Abstract: Apparatus monitors RF return current to maximize the AC signal of impedance at two return electrodes. A transformer with driving and driven windings isolates ESU and patient. At ends of the driving winding are signal and ground terminals joined to the return electrodes with capacitors returning current. An AC coupling capacitor at the signal terminal has a timing circuit in sync to the voltage wave and relative to impedance of the return electrodes. Microprocessing the voltage at the signal terminal of the driving winding watches impedance and determines if the RF return current path is adequate. Voltage detection within the timing circuit has a voltage shaping circuit. A voltage comparator after the voltage detection forms a square wave. A current detection circuit and a coupling capacitor allow AC flow to the driving winding. Current shaping circuit in the current detection circuit has a voltage comparator at the output to form a square wave. Phase detection at the voltage and current detection circuits outputs filters the phase difference that is sampled and held as DC input to a switch, with an output and a few inputs to DC voltages. Phase locking an oscillating voltage source directly and/or through the sample and hold or DC switch tunes oscillation frequency and maximizes the voltage detection circuit output. Monitoring the return current with a signal from the voltage detection circuit connected to an oscillating voltage that is phase locked to the current phase therein shows that no phase difference and maximum signal voltage occur simultaneously.
783 citations
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TL;DR: This work presents the experimental realization of a position transducer integrated with a mechanical resonator, yielding an unequalled displacement sensitivity of 2 × 10-15 m Hz-1/2 for a 116-MHz mechanical oscillator at a temperature of 30’mK—a sensitivity roughly a factor of 100 larger than the quantum limit for this oscillator.
Abstract: It has been a long-standing goal to detect the effects of quantum mechanics on a macroscopic mechanical oscillator. Position measurements of an oscillator are ultimately limited by quantum mechanics, where 'zero-point motion' fluctuations in the quantum ground state combine with the uncertainty relation to yield a lower limit on the measured average displacement. Development of a position transducer, integrated with a mechanical resonator, that can approach this limit could have important applications in the detection of very weak forces, for example in magnetic resonance force microscopy and a variety of other precision experiments. One implementation that might allow near quantum-limited sensitivity is to use a single electron transistor (SET) as a displacement sensor: the exquisite charge sensitivity of the SET at cryogenic temperatures is exploited to measure motion by capacitively coupling it to the mechanical resonator. Here we present the experimental realization of such a device, yielding an unequalled displacement sensitivity of 2 x 10(-15) m x Hz(-1/2) for a 116-MHz mechanical oscillator at a temperature of 30 mK-a sensitivity roughly a factor of 100 larger than the quantum limit for this oscillator.
548 citations
Patent•
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TL;DR: In this paper, a multi-touch capacitive touch sensor panel can be created using a substrate with column and row traces formed on either side of the substrate to shield the column (sense) traces from the effects of capacitive coupling from a modulated Vcom layer in an adjacent liquid crystal display (LCD).
Abstract: A multi-touch capacitive touch sensor panel can be created using a substrate with column and row traces formed on either side of the substrate. To shield the column (sense) traces from the effects of capacitive coupling from a modulated Vcom layer in an adjacent liquid crystal display (LCD) or any source of capacitive coupling, the row traces can be widened to shield the column traces, and the row traces can be placed closer to the LCD. In particular, the rows can be widened so that there is spacing of about 30 microns between adjacent row traces. In this manner, the row traces can serve the dual functions of driving the touch sensor panel, and also the function of shielding the more sensitive column (sense) traces from the effects of capacitive coupling.
478 citations
Patent•
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TL;DR: In this article, a technique of forming capacitive coupling between the floating gate and an erase gate in a flash EEPROM array cell with improved endurance is disclosed, which allows the density of the array to be increased since the amount of semiconductor substrate area occupied by each cell is decreased without having to sacrifice the amount or quality of the capacitance.
Abstract: A memory array of PROM, EPROM or EEPROM cells has each cell formed in a trench of a thick oxide layer deposited on a silicon substrate, in a manner that a significant portion of opposing areas of the floating gate and control gate of each cell which provide capacitive coupling between them are formed vertically. This allows the density of the array to be increased since the amount of semiconductor substrate area occupied by each cell is decreased without having to sacrifice the amount or quality of the capacitive coupling. Further, a technique of forming capacitive coupling between the floating gate and an erase gate in a flash EEPROM array cell with improved endurance is disclosed.
468 citations
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IBM1
TL;DR: In this paper, the authors analyzed short, medium, and long on-chip interconnections having linewidths of 0.45-52 /spl mu/m in a five-metal-layer structure.
Abstract: Short, medium, and long on-chip interconnections having linewidths of 0.45-52 /spl mu/m are analyzed in a five-metal-layer structure. We study capacitive coupling for short lines, inductive coupling for medium-length lines, inductance and resistance of the current return path in the power buses, and line resistive losses for the global wiring. Design guidelines and technology changes are proposed to achieve minimum delay and contain crosstalk for local and global wiring. Conditional expressions are given to determine when transmission-line effects are important for accurate delay and crosstalk prediction.
391 citations