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Carry (arithmetic)

About: Carry (arithmetic) is a(n) research topic. Over the lifetime, 1635 publication(s) have been published within this topic receiving 16018 citation(s).

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Papers
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Journal ArticleDOI: 10.1109/TEC.1961.5219227
Algirdas Avizienis1Institutions (1)
Abstract: This paper describes a class of number representations which are called signed-digit representations. Signed-digit representations limit carry-propagation to one position to the left during the operations of addition and subtraction in digital computers. Carry-propagation chains are eliminated by the use of redundant representations for the operands. Redundancy in the number representation allows a method of fast addition and subtraction in which each sum (or difference) digit is the function only of the digits in two adjacent digital positions of the operands. The addition time for signed-digit numbers of any length is equal to the addition time for two digits. The paper discusses the properties of signed-digit representations and arithmetic operations with signed-digit numbers: addition, subtraction, multiplication, division and roundoff. A brief discussion of logical design problems for a signed-digit adder concludes the presentation.

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Topics: Carry (arithmetic) (63%), Redundant binary representation (61%), Multiplication (59%) ...read more

1,202 Citations


Journal ArticleDOI: 10.1109/IRETELC.1962.5407919
O. J. Bedrij1Institutions (1)
Abstract: A large, extremely fast digital adder with sum selection and multiple-radix carry is described. Boolean expressions for the operation are included. The amount of hardware and the logical delay for a 100-bit ripple-carry adder and a carry-select adder are compared. The adder system described increases the speed of the addition process by reducing the carry-propagation time to the minimum commensurate with economical circuit design. The problem of carry-propagation delay is overcome by independently generating multiple-radix carries and using these carries to select between simultaneously generated sums. In this adder system, the addend and augend are divided into subaddend and subaugend sections that are added twice to produce two subsums. One addition is done with a carry digit forced into each section, and the other addition combines the operands without the forced carry digit. The selection of the correct, or true, subsum from each of the adder sections depends upon whether or not there actually is a carry into that adder section.

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Topics: Carry-select adder (80%), Adder (79%), Carry-save adder (78%) ...read more

419 Citations


Open accessPosted Content
Abstract: We present a new linear-depth ripple-carry quantum addition circuit. Previous addition circuits required linearly many ancillary qubits; our new adder uses only a single ancillary qubit. Also, our circuit has lower depth and fewer gates than previous ripple-carry adders.

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Topics: Serial binary adder (74%), Adder (73%), Carry-save adder (73%) ...read more

327 Citations


Open accessJournal ArticleDOI: 10.3233/SAT190012
Abstract: In order to facilitate automated reasoning about large Boolean combinations of nonlinear arithmetic constraints involving transcendental functions, we provide a tight integration of recent SAT solving techniques with interval-based arithmetic constraint solving. Our approach deviates substantially from lazy theorem proving approaches in that it directly controls arithmetic constraint propagation from the SAT solver rather than delegating arithmetic decisions to a subordinate solver. Through this tight integration, all the algorithmic enhancements that were instrumental to the enormous performance gains recently achieved in propositional SAT solving carry over smoothly to the rich domain of nonlinear arithmetic constraints. As a consequence, our approach is able to handle large constraint systems with extremely complex Boolean structure, involving Boolean combinations of multiple thousand arithmetic constraints over some thousands of variables.

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316 Citations


Patent
Bernard J. New1Institutions (1)
31 Aug 1994-
Abstract: Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things, for performing arithmetic functions which use logic for generating the carry function. When a large number of bits is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed. The present invention provides dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components. The invention takes advantage of the fact that a carry signal to be added to two bits can be propagated to the next more significant bit when the two binary bits to be added are unequal, and that one of the bits can serve as the carry signal when the bits are equal. For each bit, a carry propagate signal is generated by a lookup table programmable function generator and is used by dedicated hardware to generate the carry signal.

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Topics: Carry flag (64%), Bit field (61%), Programmable logic device (58%) ...read more

243 Citations


Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20222
202124
202032
201932
201835
201728

Top Attributes

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Topic's top 5 most impactful authors

Karl M. Guttag

5 papers, 240 citations

DC Blest

4 papers, 39 citations

J. Arjun Prabhu

4 papers, 119 citations

Earl E. Swartzlander

4 papers, 52 citations

Holger Sedlak

3 papers, 1 citations

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