Carry flag

About: Carry flag is a research topic. Over the lifetime, 346 publications have been published within this topic receiving 3543 citations. The topic is also known as: C flag.

Logic structure and circuit for fast carry

Abstract: Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things, for performing arithmetic functions which use logic for generating the carry function. When a large number of bits is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed. The present invention provides dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components. The invention takes advantage of the fact that a carry signal to be added to two bits can be propagated to the next more significant bit when the two binary bits to be added are unequal, and that one of the bits can serve as the carry signal when the bits are equal. For each bit, a carry propagate signal is generated by a lookup table programmable function generator and is used by dedicated hardware to generate the carry signal.

Superscaler microprocessor including flag operand renaming and forwarding apparatus

Abstract: A superscalar microprocessor is provided with a reorder buffer for storing the speculative state of the microprocessor and a register file for storing the real state of the microprocessor. A flags register stores the real state of flags that are updated by flag modifying instructions which are executed by the functional units of the microprocessor. To enhance the performance of the microprocessor with respect to conditional branching instructions, the reorder buffer includes a flag storage area for storing flags that are updated by flag modifying instructions. The flags are renamed to make possible the earlier execution of branch instructions which depend on flag modifying instructions. If a flag is not yet determined, then a flag tag is associated with the flag storage area in place of that flag until the actual flag value is determined. A flag operand bus and a flag tag bus are provided between the flag storage area and the branching functional unit so that the requested flag or flag tags are provided to instructions which are executed in the branching functional unit.

Method and apparatus for configuring arbitrary sized data paths comprising multiple context processing elements

Abstract: A method and an apparatus for configuring arbitrary sized data paths comprising multiple context processing elements (MCPEs) are provided. Multiple MCPEs may be chained to form wider-word data paths of arbitrary widths, wherein a first ALU serves as the most significant byte (MSB) of the data path while a second ALU serves as the least significant byte (LSB) of the data path. The ALUs of the data path are coupled using a left-going, or forward, carry chain for transmitting at least one carry bit from the LSB ALU to the MSB ALU. The MSB ALU comprises configurable logic for generating at least one signal in response to a carry bit received over the left-going carry chain, the at least one signal comprising a saturation signal and a saturation value. The MCPEs of the data path use configurable logic to manipulate a resident bit sequence in response to the saturation signal transmitted thereby reconfiguring, or changing the operation of, the data path in response to the saturation signal. The carry chains support carry operations for non-local functions comprising minimum and maximum arithmetic functions.

System for controlling synchronization in a digital communication system

Abstract: A technique and implementation of generating and supplying synchronization and error checking signals to a serially transmitted data stream includes the generation of flag bytes which define the end boundaries of the serial data stream, an abort character for aborting the transmission of a frame of data in response to certain conditions, and a diagnostic evaluation character inserted into the data stream. In addition, the invention provides a technique for ensuring that the unique binary code by which a flag byte is defined occurs in the transmitted data stream only where intended. The flag code has been chosen to contain a prescribed number of consecutive one bits, (i.e. -- six) flanked by zeroes, and circuitry monitors the contents of a data frame as it is being serialized out for transmission to a remote terminal at times other than during flag transmission. When five consecutive one bits are detected, serializing out of the next bit in the data is interrupted, and a dummy zero bit is inserted prior to the next bit. As a result, the transmitted frame of data will contain no more than five consecutive one bits, except during the flag bytes, (or an abort character) thus ensuring proper synchronization of the end points of the frame. At the receiver terminal, detection and decoding circuitry also monitors the number of consecutive one's in the received data stream. When five consecutive one's are detected, the receiver decoder circuitry checks to see whether the next bit is a dummy zero bit. If the next bit is a zero bit, it is deleted so that the intended data will be correctly reassembled.

Merge/mask, rotate/shift, and boolean operations from two instruction sets executed in a vectored mux on a dual-ALU

Abstract: A Boolean logic unit (BLU) features a vectored mux. Boolean instructions are executed by applying operands to the select inputs but truth-table signals to the data inputs. Merge and mask operations are performed by reversing the connection and inputting the operands to the data inputs but applying a merge mask to the select inputs. A byte-spreader copies byte or 16-bit operands to 32-bits before being rotated and merged by the vectored mux. A rotator is used to rotate an operand before being applied to the data input of the vectored mux so that compound rotate-merge operations can be executed in a single step through the vectored mux. A carry flag may also be merged in during a multi-step bit-test instruction. Complex CISC instructions such as rotate-through-carry and shift-double are executed in multiple steps on the vectored mux. Intermediate results are stored in the multiplier-quotient temporary registers which are normally used for multiply and divide instructions. A RISC ALU using the vectored mux BLU is modified only slightly to support execution of CISC instructions. Merge, mask, rotate, shift, and Boolean operations of both RISC and CISC instruction sets are executed in the same ALU because of the inherent flexibility of the vectored mux architecture.