Carry-lookahead adder

About: Carry-lookahead adder is a(n) research topic. Over the lifetime, 243 publication(s) have been published within this topic receiving 3794 citation(s).

Adder Designs and Analyses for Quantum-Dot Cellular Automata

Abstract: Quantum-dot cellular automata (QCA) is an emerging nanotechnology for electronic circuits. Its advantages such as faster speed, smaller size, and lower power consumption are very attractive. The fundamental device, a quantum-dot cell, can be used to make gates, wires, and memories. As such it is the basic building block of nanotechnology circuits. While the physical nature of the nanoscale materials is complicated, the circuit designer can concentrate on the logical and structural design, so the design effort is reduced. Because of its novelty, the current literature shows only simple circuit structures. So this paper broadens the QCA circuit designs with larger circuits and shows analyses based on those designs. This paper proposes three kinds of adder designs in QCA. Ripple carry adders, carry lookahead adders, and conditional sum adders are designed and simulated with several different operand sizes. The designs are compared according to complexity, area, and delay

Area-time-power tradeoffs in parallel adders

Abstract: In this paper, several classes of parallel, synchronous adders are surveyed based on their power, delay and area characteristics. The adders studied include the linear time ripple carry and Manchester carry chain adders, the square-root time carry skip and carry select adders, the logarithmic time carry lookahead adder and its variations, and the constant time signed-digit and carry-save adders. Most of the research in the last few decades has concentrated on reducing the delay of addition. With the rising popularity of portable computers, however, the emphasis is on both high speed and low power operation. In this paper we adopt a uniform static CMOS layout methodology whereby short circuit power mininization is used as the optimization criterion. The relative merits of the different adders are evaluated by performing a detailed transistor-level simulation of the adders using HSPICE. Among the two's complement adders, a variation of the carry lookahead adder, called ELM, was found to have the best power-delay product. Based on the results of our experiments, a large adder design space is formulated from which an architect can choose an adder with the desired characteristics.

A logarithmic-depth quantum carry-lookahead adder

Abstract: We present an efficient addition circuit, borrowing techniques from classical carry-lookahead arithmetic. Our quantum carry-lookahead (QCLA) adder accepts two n-bitnumbers and adds them in O(log n) depth using O(n) ancillary qubits. We present bothin-place and out-of-place versions, as well as versions that add modulo 2n and modulo2n - 1. Previously, the linear-depth ripple-carry addition circuit has been the methodof choice. Our work reduces the cost of addition dramatically with only a slight increasein the number of required qubits. The QCLA adder can be used within current modularmultiplication circuits to reduce substantially the run-time of Shor's algorithm.

A 4.4 ns CMOS 54/spl times/54-b multiplier using pass-transistor multiplexer

Abstract: A 54/spl times/54-b multiplier using pass-transistor multiplexers has been fabricated by 0.25 /spl mu/m CMOS technology. To enhance the speed performance, a new 4-2 compressor and a carry lookahead adder (CLA), both featuring pass-transistor multiplexers, have been developed. The new circuits have a speed advantage over conventional CMOS circuits because the number of critical-path gate stages is minimized due to the high logic functionality of pass-transistor multiplexers. The active size of the 54/spl times/54-b multiplier is 3.77/spl times/3.41 mm. The multiplication time is 4.4 ns at a 3.5-V power supply. >

A spanning tree carry lookahead adder

Abstract: The design of the 56-b significant adder used in the Advanced Micro Devices Am29050 microprocessor is described. Originally implemented in a 1- mu m design role CMOS process, it evaluates 56-b sums in well under 4 ns. The adder employs a novel method for combining carries which does not require the back propagation associated with carry lookahead, and is not limited to radix-2 trees, as is the binary lookahead carry tree of R.P. Brent and H.T. Kung (1982). The adder also utilizes a hybrid carry lookahead-carry select structure which reduces the number of carriers that need to be derived in the carry lookahead tree. This approach produces a circuit well suited for CMOS implementation because of its balanced load distribution and regular layout. >