Showing papers on "Carry-lookahead adder published in 1972"
Patent•
30 Oct 1972
TL;DR: Disclosed as discussed by the authors is an adder for use in a data processing system which includes five levels of logic circuits for forming bit propagate, bit generate, group propagate, half-sum internal carry and full-sum terms.
Abstract: Disclosed is an adder for use in a data processing system. The adder includes five levels of logic circuits for forming bit propagate, bit generate, group propagate, half-sum internal carry and full-sum terms. Additionally, redundancy Z terms are introduced which, together with bunch propagates and bunch generates produce external carries which are combined to generate the full-sum terms. The inclusion of redundancy in terms enables a factoring of terms which reduces the fan-in and fan-out requirements within the adder.
18 citations